Sony MDS-NT1 Service Manual ▷ View online
53
MDS-NT1
Pin No.
Pin Name
I/O
Description
41
A11
O
Address signal output to the external D-RAM Not used
42 to 45
D0 to D3
I/O
Two-way data bus with the D-RAM
46
XCAS
O
Column address strobe signal output to the D-RAM “L” active
47
XRAS
O
Row address strobe signal output to the D-RAM “L” active
48 to 56
A00 to A02,
A05 to A10
O
Address signal output to the D-RAM
57
VDC2
—
Power supply terminal (+2.5V) (for core)
58
VSC2
—
Ground terminal (for core)
59, 60
A03, A04
O
Address signal output to the D-RAM
61
DRVDD1
—
Power supply terminal (+3.3V) (for D-RAM interface)
62
DRVSS1
—
Ground terminal (for D-RAM interface)
63, 64
TEST0, TEST1
I
Not used
65
TEST2
O
Not used
66
AVD1
—
Power supply terminal (+3.3V) (analog system)
67
ASYO
O
Playback EFM full-swing output
68
ASYI
I
Playback EFM comparator slice voltage input
69
BIAS
I
Playback EFM comparator bias current input
70
RFI
I
Playback EFM RF signal input from the RF amplifier
71
AVS1
—
Ground terminal (analog system)
72
PCO
O
Phase comparison output for master clock of the recording/playback EFM master PLL
73
FILI
I
Filter input for master clock of the recording/playback EFM master PLL
74
FILO
O
Filter output for master clock of the recording/playback EFM master PLL
75
CLTV
I
Internal VCO control voltage input of the recording/playback EFM master PLL
76
PEAK
I
Light amount signal (RF/ABCD) peak hold input from the RF amplifier
77
BOTM
I
Light amount signal (RF/ABCD) bottom hold input from the RF amplifier
78
ABCD
I
Light amount signal (ABCD) input from the RF amplifier
79
FE
I
Focus error signal input from the RF amplifier
80
AUX1
I
Auxiliary signal (I
3
signal/temperature signal) input from the RF amplifier
81
VC
I
Middle point voltage (+1.65V) input from the RF amplifier
82
ADIO
O
Output terminal for the test
83
ADRT
I
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
84
ADRB
I
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
85
SE
I
Sled error signal input from the RF amplifier
86
TE
I
Tracking error signal input from the RF amplifier
87
AVD2
—
Power supply terminal (+3.3V) (analog system)
88
AVS2
—
Ground terminal (analog system)
89
DCHG
I
Connected to the +3.3V power supply
90
APC
I
Error signal input terminal for laser digital automatic power control Not used
91
ADFG
I
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the RF amplifier
92
VDIO1
—
Power supply terminal (+3.3V) (for I/O)
93
VSIO1
—
Ground terminal (for I/O)
94
F0CN
O
Filter f0 control signal output to the RF amplifier
95
VDC3
—
Power supply terminal (+2.5V) (for core)
96
VSC3
—
Ground terminal (for core)
97
XLRF
O
Serial data latch pulse signal output to the RF amplifier
98
CKRF
O
Serial data transfer clock signal output to the RF amplifier
99
DTRF
O
Writing serial data output to the RF amplifier
54
MDS-NT1
Pin No.
Pin Name
I/O
Description
100
APC
O
Reference PWM signal output to the RF amplifier for the laser automatic power control
101
LDDR
O
PWM signal output terminal for laser digital automatic power control Not used
102
TRDR
O
Tracking servo drive PWM signal (–) output
103
TFDR
O
Tracking servo drive PWM signal (+) output
104
FFDR
O
Focus servo drive PWM signal (+) output
105
FRDR
O
Focus servo drive PWM signal (–) output
106
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used
107
SRDR
O
Sled servo drive PWM signal (–) output
108
SFDR
O
Sled servo drive PWM signal (+) output
109
SPRD
O
Spindle servo drive PWM signal (–) output
110
SPFD
O
Spindle servo drive PWM signal (+) output
111
FGIN
I
FG input terminal for spindle servo Not used
112 to 114
TST1 to TST3
I
Input terminal for the test
115
EFMO
O
EFM signal output terminal when recording mode “L” is output when playback mode
116
VDIO1
—
Power supply terminal (+3.3V) (for I/O)
117
VSIO1
—
Ground terminal (for I/O)
118
VDC4
—
Power supply terminal (+2.5V) (for core)
119
VSC4
—
Ground terminal (for core)
120
MDDT1
I
MD data mode selection signal input terminal
“L”: normal mode, “H”: MD data mode (fixed at “L” in this set)
“L”: normal mode, “H”: MD data mode (fixed at “L” in this set)
55
MDS-NT1
•
MAIN BOARD IC301 M30823MH-050FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NC
—
Not used
2
RMC
I
Remote control signal input terminal Not used
3
NETMD_SO
O
Serial data output to the USB interface IC
4
NETMD_SI
I
Serial data input from the USB interface IC
5
NETMD_CLK
O
Serial data transfer clock output to the USB interface IC
6
BYTE
I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
7
CNVSS
—
Not used
8, 9
NC
—
Not used
10
S.RESET
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
11
XOUT
I
System clock input terminal (10 MHz)
12
VSS
—
Ground terminal
13
XIN
O
System clock output terminal (10 MHz)
14
VCC
—
Power supply terminal (+3.3V)
15
NMI
I
Non-maskable interrupt input terminal Not used
16
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input terminal
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
17
P.DOWN
I
Power down detection signal input terminal
20
SQSY
I
Subcode Q sync (SCOR) input terminal
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
19 to 22
NC
—
Not used
23
XINT
I
Interrupt status input from the mechanism deck section
24 to 26
NC
—
Not used
27
I2C_CLK
I/O
Communication data reading clock signal output terminal Not used
28
I2C_DATA
I/O
Communication data bus input/output terminal Not used
29
SWDT
O
Writing data output to the mechanism deck section and the D/A converter
30
SRDT
I
Reading data input from the mechanism deck section
31
SCLK
O
Serial data transfer clock signal output to the mechanism deck section and the D/A converter
32
RTSI
—
Not used
33 to 35
NC
—
Not used
36
MUTE
O
Audio line muting control signal output terminal “L”: line muting on
37
ADA_RESET
O
Reset signal output to the D/A converter “L”: reset
38
ADA_LATCH
O
Serial data latch signal output to the D/A converter “L”: reset
39
EPM
—
Not used
40, 41
NC
—
Not used
42
MOD
O
Laser modulation select signal output terminal Stop: “L” Playback power: “H”
Recoding power: “H” pulse is inputted in a cycle of 2 seconds
Recoding power: “H” pulse is inputted in a cycle of 2 seconds
43
LDON
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
44
CE
I
Command chip enable signal output to the D-RAM
45
LIMIT-IN
I
Detection input from the sled limit-in detect switch (S101)
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
46
WRPWR
O
Laser power select signal output terminal “L”: playback mode, “H”: recording mode
47
REC-SW
I
Detection input from the recording position detect switch “L”: active
48
ADA_RESET
O
Reset signal output to the mechanism deck section “L”: reset
49
SENSE
I
Internal status (SENSE) signal input to the mechanism deck section
Ver 1.1
56
MDS-NT1
Pin No.
Pin Name
I/O
Description
50
PLAY-SW
I
Detection input from the playback position detect switch “L”: active
51
XLATCH
O
Serial data latch pulse signal output to the mechanism deck section
52
SCL
O
Serial clock signal output to the EEPROM
53
OUT-SW
I
Detection signal input from the loading-out detect switch (S103)
“L” at a load-out position, others: “H”
“L” at a load-out position, others: “H”
54
XBUSY
I
Busy monitor signal input from the mechanism deck section
55
SHOCK
I
Track jump detection signal input from the mechanism deck section
56
EEP-WP
O
Writing protect signal output to the EEPROM
57
SDA
I/O
Two-way data bus with the EEPROM
58
REFLECT
I
Detection input from the disc reflection rate detect switch
“L”: high reflection rate disc, “H”: low reflection rate disc
“L”: high reflection rate disc, “H”: low reflection rate disc
59
PROTECT SW
I
REC-proof claw detection signal input from the protect detect switch
“H”: write protect
“H”: write protect
60
VCC
—
Power supply terminal (+3.3V)
61
EEPNET-WP
—
Not used
62
VSS
—
Ground terminal
63
LD-LOW
O
Loading motor drive voltage control signal output terminal “H” active
64
LOAD OUT
O
Loading motor control signal (load-in direction) output terminal “H” at a load-in
65
LOAD OUT
O
Loading motor control signal (eject direction) output terminal “H” at a eject
66 to 69
TEST
I
Test input terminal Not used
70 to 72
NC
—
Not used
73
NETMD_INT
I
Interrupt status input from the USB interface IC
74
NETMD_XCS
O
Chip select signal output to the USB interface IC
75
NETMD_RESET
O
Reset signal output to the USB interface IC “L”: reset
76
NETMD_PLLSW
O
PLL function on/off control signal output to the USB interface IC “L”: PLL on
77
NETMD_VBUS
I
USB connect detection signal input terminal “H”: USB on
78, 79
NC
—
Not used
80
LED4
O
LED drive signal output terminal Not used
81, 82
LED3, 2
O
LED drive signal output terminal
83
FLCS
—
Not used
84
LED1
O
LED drive signal output terminal
85
JOG0
I
Jog dial pulse input terminal Not used
86
JOG1
I
Jog dial pulse input terminal Not used
87
IOP
—
Not used
88
SEL1
I
Destination setting terminal
89
SEL0
I
Model setting terminal
90, 91
NC
—
Not used
92
KEY2
I
key input terminal Not used
93
KEY1
I
B/> key input terminal
94
AVSS
—
Ground terminal
95
KEY0
I
x/Z key input terminal
96
VREF
I
Reference voltage (+3.3V) input terminal
97
AVCC
—
Power supply terminal (+3.3V)
98
NC
—
Not used
99
FLDT
—
Not used
100
FLCK
—
Not used
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