DOWNLOAD Sony HT-ST3 Service Manual ↓ Size: 5.48 MB | Pages: 78 in PDF or view online for FREE

Model
HT-ST3
Pages
78
Size
5.48 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
ht-st3.pdf
Date
PREV: Sony NWZ-W273S / NWZ-W274S Service Manual

Sony HT-ST3 Service Manual ▷ View online

HT-ST3
53
Pin No.
Pin Name
I/O
Description
129
MUTEOUT
O
HDMI muting on/off control signal output terminal    “H”: muting on
130
SPDIF0_OUT
O
S/PDIF audio signal output to the digital audio interface receiver
131, 132
GPIO11, GPIO10
I/O
Not used
133
SPDIFO_IN
I
S/PDIF audio signal input terminal    Not used
134
SCK1_OUT
O
Serial data transfer clock signal output terminal    Not used
135
WS1_OUT
O
Word select signal output terminal    Not used
136
SPDIF1_OUT
O
S/PDIF audio signal output to the digital audio interface receiver
137
ARC0
I
Digital audio signal input from the HDMI OUT TV ARC connector
138
ARC1
I
Digital audio signal input terminal    Not used
139
CVCC12
-
Power supply terminal (+1.3V)
140
TPVDD12
-
Power supply terminal (+1.3V)
141
TDVDD12
-
Power supply terminal (+1.3V)
142
T1XC–
O
TMDS clock (negative) output to the HDMI OUT TV ARC connector
143
T1XC+
O
TMDS clock (positive) output to the HDMI OUT TV ARC connector
144
T1X0–
O
TMDS data (negative) output to the HDMI OUT TV ARC connector
145
T1X0+
O
TMDS data (positive) output to the HDMI OUT TV ARC connector
146
T1X1–
O
TMDS data (negative) output to the HDMI OUT TV ARC connector
147
T1X1+
O
TMDS data (positive) output to the HDMI OUT TV ARC connector
148
T1X2–
O
TMDS data (negative) output to the HDMI OUT TV ARC connector
149
T1X2+
O
TMDS data (positive) output to the HDMI OUT TV ARC connector
150
TPVDD12
-
Power supply terminal (+1.3V)
151
TDVDD12
-
Power supply terminal (+1.3V)
152
T0XC–
O
TMDS clock (negative) output terminal    Not used
153
T0XC+
O
TMDS clock (positive) output terminal    Not used
154
T0X0–
O
TMDS data (negative) output terminal    Not used
155
T0X0+
O
TMDS data (positive) output terminal    Not used
156
T0X1–
O
TMDS data (negative) output terminal    Not used
157
T0X1+
O
TMDS data (positive) output terminal    Not used
158
T0X2–
O
TMDS data (negative) output terminal    Not used
159
T0X2+
O
TMDS data (positive) output terminal    Not used
160
CVCC12
-
Power supply terminal (+1.3V)
161 to 171
D0 to D10
I
Digital video signal input terminal    Not used
172
IDCK
I
Output data clock signal input terminal    Not used
173
IOVCC33
-
Power supply terminal (+3.3V)
174 to 176
D11 to D13
I
Digital video signal input terminal    Not used
HT-ST3
54
AMP  BOARD  IC5001  ADSST-AVR-3046 (DSP)
Pin No.
Pin Name
I/O
Description
1
SDDQM
O
Data mask signal output to the SD-RAM
2
MS0
O
Memory selection signal output to the SD-RAM
3
SDCKE
O
Clock enable signal output to the SD-RAM
4
VDD_INT
-
Power supply terminal (+1.1V) (for core)
5
CLK_CFG1
I
Core instruction rate to CLKIN (pin 24) ratio selection signal input terminal    
Fixed at “L” in this unit
6
ADDR0
O
Address signal output to the SD-RAM
7
BOOT_CFG0
I
Boot mode selection signal input terminal    Fixed at “H” in this unit
8
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
9 to 13
ADDR1 to ADDR5
O
Address signal output to the SD-RAM
14
BOOT_CFG1
I
Serial data input from the system controller
15
GND
-
Ground terminal
16, 17
ADDR6, ADDR7
O
Address signal output to the SD-RAM
18, 19
NC
-
Not used
20, 21
ADDR8, ADDR97
O
Address signal output to the SD-RAM
22
CLK_CFG0
I
Core instruction rate to CLKIN (pin 24) ratio selection signal input terminal    
Fixed at “L” in this unit
23
VDD_INT
-
Power supply terminal (+1.1V) (for core)
24
CLKIN
I
System clock input terminal (25 MHz)
25
XTAL2
O
System clock output terminal (25 MHz)
26
ADDR10
O
Address signal output terminal    Not used
27
SDA10
O
Address signal output to the SD-RAM
28
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
29
VDD_INT
-
Power supply terminal (+1.1V) (for core)
30
ADDR11
O
Address signal output to the SD-RAM
31
ADDR12
O
Address signal output terminal    Not used
32
ADDR17
O
Bank address signal output to the SD-RAM
33
ADDR13
O
Address signal output terminal    Not used
34
VDD_INT
-
Power supply terminal (+1.1V) (for core)
35
ADDR18
O
Bank address signal output to the SD-RAM
36
RESETOUT/
RUNRSTIN
I/O
Reset signal output and running reset signal input terminal    Not used
37
VDD_INT
-
Power supply terminal (+1.1V) (for core)
38
MOSI
I
Serial data input from the system controller
39
MISO
O
Serial data output to the system controller
40
SPICLK
I
Serial data transfer clock signal input from the system controller
41
VDD_INT
-
Power supply terminal (+1.1V) (for core)
42
DPI_P05
I
Chip select signal input from the system controller
43
DSP_CS
I
Chip select signal input from the system controller
44
MD
-
Not used
45
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
46
NC
-
Not used
47
RESET_MAIN
-
Not used
48
VDD_INT
-
Power supply terminal (+1.1V) (for core)
49
UART_OUT
O
Serial data output to the system controller
50
UART_IN
I
Serial data input from the system controller
51
LED
-
Not used
52 to 56
NC
-
Not used
57
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
58 to 61
NC
-
Not used
62
VDD_INT
-
Power supply terminal (+1.1V) (for core)
63, 64
NC
-
Not used
65
VDD_INT
-
Power supply terminal (+1.1V) (for core)
66, 67
NC
-
Not used
68
VDD_INT
-
Power supply terminal (+1.1V) (for core)
69
NC
-
Not used
70
WDTRSTO
O
Watchdog timer reset signal output terminal    Not used
71
NC
-
Not used
72
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
HT-ST3
55
Pin No.
Pin Name
I/O
Description
73
SL/SR_OUT
O
Audio signal (for surround L-ch/R-ch) output to the stream processor
74
SL/SR_IN
I
Audio signal (for surround L-ch/R-ch) input from the digital audio interface receiver
75
BCLK_IN
I
Bit clock signal input from the digital audio interface receiver
76
OPTION_L/
OPTION_R_OUT
O
Audio signal output terminal    Not used
77
FRONTHI_L/R_OUT
O
Audio signal output terminal    Not used
78
VDD_INT
-
Power supply terminal (+1.1V) (for core)
79 to 83
NC
-
Not used
84
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
85
VDD_INT
-
Power supply terminal (+1.1V) (for core)
86
L/R_OUT
O
Audio signal (for front L-ch/R-ch) output to the stream processor
87
MID/SW2_OUT
O
Audio signal output terminal    Not used
88
SBL/SBR_OUT
O
Audio signal (for surround back L-ch/R-ch) output to the stream processor
89
ZONE_L/R
I/O
Not used
90
VDD_INT
-
Power supply terminal (+1.1V) (for core)
91
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
92
MCLK_IN
I
Master clock signal input from the digital audio interface receiver
93
VDD_INT
-
Power supply terminal (+1.1V) (for core)
94
C/SW_OUT
O
Audio signal (for center and subwoofer) output to the stream processor
95
C/SW_IN
I
Audio signal (for center and subwoofer) input from the digital audio interface receiver
96
A/D_2CH
I
Audio signal input from the digital audio interface receiver
97
LRCLK_IN
I
L/R sampling clock signal input from the digital audio interface receiver
98
BCLK_OUT
O
Bit clock signal output to the stream processor
99
LRCLK_OUT
O
L/R sampling clock signal output to the stream processor
100
L/R_IN
I
Audio signal (for front L-ch/R-ch) input from the digital audio interface receiver
101
SBL/SBR_IN
I
Audio signal (for surround back L-ch/R-ch) input from the digital audio interface receiver
102
VDD_INT
-
Power supply terminal (+1.1V) (for core)
103
DIR_IN
I
Audio signal input from the digital audio interface receiver
104
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
105
VDD_INT
-
Power supply terminal (+1.1V) (for core)
106
BOOT_CFG2
I
Boot mode selection signal input terminal    Fixed at “L” in this unit
107
VDD_INT
-
Power supply terminal (+1.1V) (for core)
108
AMI_ACK
I
Acknowledge signal input terminal    Not used
109
GND
-
Ground terminal
110
THD_M
O
Thermal detection signal output terminal    Not used
111
THD_P
I
Thermal detection signal input terminal    Not used
112
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
113, 114
VDD_INT
-
Power supply terminal (+1.1V) (for core)
115
MS1
O
Memory selection signal output terminal    Not used
116
VDD_INT
-
Power supply terminal (+1.1V) (for core)
117
WDT_CLKO
O
Watchdog timer clock signal output terminal    Not used
118
WDT_CLKIN
I
Watchdog timer clock signal input terminal    Not used
119
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
120 to 
122
ADDR23 to ADDR21
O
Address signal output terminal    Not used
123
VDD_INT
-
Power supply terminal (+1.1V) (for core)
124, 125
ADDR20,  ADDR19
O
Address signal output terminal    Not used
126
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
127, 128
ADDR16, ADDR15
O
Address signal output terminal    Not used
129
VDD_INT
-
Power supply terminal (+1.1V) (for core)
130
ADDR14
O
Address signal output terminal    Not used
131
AMI_WR
O
Write enable signal output terminal    Not used
132
AMI_RD
O
Read enable signal output terminal    Not used
133
VDD_INT
-
Power supply terminal (+1.1V) (for core)
134
IRQ
O
Interrupt request signal output to the system controller
135
FLAG1
I
Error detection signal input terminal    “L”: error
136
FLAG2
I
Audio setting signal input terminal    “L”: LPCM audio, “H”: HBR audio
137
MLBCLK
I
Media local bus clock signal input terminal    Not used
138
FLAG3
-
Not used
139
MLBDAT
I/O
Two-way media local bus data terminal    Not used
HT-ST3
56
Pin No.
Pin Name
I/O
Description
140
MLBDO
O
Media local bus data output terminal    Not used
141
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
142
MLBSIG
I/O
Two-way media local bus signal terminal    Not used
143
VDD_INT
-
Power supply terminal (+1.1V) (for core)
144
TRST
I
Test reset signal input terminal (for JTAG)
145
MLBSO
O
Media local bus signal output terminal    Not used
146
EMU
O
Emulation status signal output terminal
147 to 
150
DATA0 to DATA3
I/O
Two-way data bus with the SD-RAM
151
TDO
O
Test data output terminal (for JTAG)
152
DATA4
I/O
Two-way data bus with the SD-RAM
153
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
154, 155
DATA5, DATA6
I/O
Two-way data bus with the SD-RAM
156
VDD_INT
-
Power supply terminal (+1.1V) (for core)
157
DATA7
I/O
Two-way data bus with the SD-RAM
158
TDI
I
Test data input terminal (for JTAG)
159
SDCLK
O
Clock signal output to the SD-RAM
160
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
161 to 
163
DATA8 to DATA10
I/O
Two-way data bus with the SD-RAM
164
TCK
I
Test clock signal input terminal (for JTAG)
165 to 
168
DATA11, DATA12, 
DATA14, DATA13
I/O
Two-way data bus with the SD-RAM
169
VDD_INT
-
Power supply terminal (+1.1V) (for core)
170
DATA15
I/O
Two-way data bus with the SD-RAM
171
SDWE
O
Write enable signal output to the SD-RAM
172
SDRAS
O
Row address signal output to the SD-RAM
173
RESET
I
Reset signal input from the system controller    “L”: reset
174
TMS
I
Test mode selection signal input terminal (for JTAG)
175
SDCAS
O
Column address signal output to the SD-RAM
176
VDD_INT
-
Power supply terminal (+1.1V) (for core)
Page of 78
Display

Click on the first or last page to see other HT-ST3 service manuals if exist.

RANDOM: