Sony HCD-ZX50MD Service Manual ▷ View online
97
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD (MD) BOARD)
Function
Pin No.
Pin Name
I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
FOK signal output to the system control (monitor output)
“H” is output when focus is on
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input)
Digital audio output (Optical output)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
98
Function
Pin No.
Pin Name
I/O
48
49
50, 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523AR (22.05 ± 1 kHz)
Filter f
0
control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
99
Function
Pin No.
Pin Name
I/O
86
87
88
89
90
91
92
93
94
95
96 to 98
99
100
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
O
—
O
O
O
O
O
O
O
I (S)
I
—
O
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
• Abbreviation
EFM: Eight to Fourteen Modulation
100
1
—
Not used.
2
—
Not used.
3
LVLI
—
Not used.
4
LVLO
—
Not used.
5
(TXD3)
—
Not used.
6
(RXD3)
—
Not used.
7
(CLK3)
—
Not used.
8
MUTE
O
Line out muting output. L: Mute
9
DARST
O
Reset signal output to the D/A converter. L: Active
10
SLICERSEL
O
IEC958 input select signal output to the D/A converter. L: CD H: MD
11
LD-LOW
O
Loading motor voltage control output L: High voltage H: Low voltage
12
LDIN
I
Loading motor control input. H: IN
13
LDOUT
O
Loading motor control output. H: OUT
14
MOD
O
Laser modulation switching signal output. L: OFF H: ON
15
BYTE
I
Data bus changed input. (Connected to ground.)
16
CNVSS
—
Ground.
17
X-CIN
O
Sub clock input. (32.768kHz) (Not used.)
18
X-COUT
O
Sub clock output. (32.768kHz) (Not used.)
19
RESET
I
System rest input. L : ON
20
XOUT
O
Main clock output. (10MHz)
21
VSS0
—
Ground.
22
XIN
I
Main clock input. (10MHz)
23
VCC0
—
Power supply. (+3.3V)
24
NMI
I
Fixed at H. (Pull-up)
25
DQSY
I
Digital in sync input. (Record system)
26
P.DOWN
I
Power down detection input. L: Power down
27
SQSY
I
ADIP (MO) sync or subcode Q (PIT) sync input from CXD2662R.(Playback system)
28
NC
—
Not used.
29
LDON
O
Laser ON/OFF control output. H: Laser ON
30
LIMIT-IN
I
Detection input from the limit switch. L: Sled limit-In H: Sled limit-Out
31
C2-PWM-B
—
Not used.
32
XINIT
I
Interrupt status input from CXD2662R.
33
—
Not used.
34
XELT
I
XELT input from DSP IC.
35
WR PWR
O
Write power ON/OFF output. L: OFF H: ON
36
IIC CLK
I/O
IIC serial clock input/output.
37
IIC DATA
I/O
IIC serial data input/output.
38
SWDT
O
Writing data signal output to the serial bus.
39
VCC1
—
Power supply. (+3.3V)
40
SRDT
I
Reading data signal input from the serial bus.
41
VSS1
—
Ground.
42
SCLK
O
Clock signal output to the serial bus.
43
REC-SW
I
Detection signal input from the recording position detection switch. L: REC
44
CLIP DTO
O
CLIP serial data output.
45
CLIPDTI
I
CLIP serial data input. (Not used.)
46
CLIP CLK
O
CLIP serial clock output. (Not used.)
47
DIG-RST
O
Digital rest signal output to the CXD2662R and motor driver. L: Reset
48
SENS
I
Internal status (SENSE) input from the CXD2662R.
49
PLAY-SW
I
Detection signal input from the playback position detection switch. L: PLAY
50
XLAT
O
Latch signal output to DSP IC.
51
OUT-SW
I
Detection signal input from the loading out detection switch.
52
—
Not used.
Function
Pin Name
Pin No.
I/O
• IC1001 M30805SGP SYSTEM CONTROL (DIGITAL BOARD)
Click on the first or last page to see other HCD-ZX50MD service manuals if exist.