Sony HCD-ZX50MD Service Manual ▷ View online
HCD-ZX50MD
89
89
7-36. SCHEMATIC DIAGRAM – POWER SUPPLY (E, MX, AR, HK, MY, SP, KR, AUS model) SECTION –
AUS
250V
250V
250V
90
90
7-37. IC BLOCK DIAGRAMS
IC101 CXA2523AR (BD (MD) BOARD)
–1
–2
+
–
IVR
BB
+
–
IVR
AA
+
–
IVR
CC
+
–
IVR
DD
+
–
IVR
+
–
EE
EE'
EFB
TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12
APCREF
11
APC
10
PD
9
F
8
E
7
D
6
C
5
B
4
A
3
VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+ –
–
+
AUXSW
COMMAND
+
–
IVR
GSW
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
–
–
–
–
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+
–
RFA1
–
–
–
–
1
2
–
–
–
–
–
1
2
2
GRVA
OFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC
EQ
EQ
DET
P-P
WBL
3T
WBL
TEMP
PBH
–
+
USROP
+
–
USRC
3T
BPF3T
PEAK3T
1
I
2
J
RFA3
PBSW
AUX
SW
IV
ESW
EBAL
100
99 98 97 96 95
94 93
EFMO
DVSS
TEST3
TEST2
TEST1
TEST0
SPFD
SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 TE
74 SE
73 AVSS
72 ADRB
71 ADRT
70 AVDD
69 ADIO
62 CLTV
61 FILO
60 FILI
59 PCO
57 RFI
58 AVSS
56 BIAS
55 AVDD
54 ASYI
53 ASYO
52 MVCI
51 D3
68 VC
67 AUX1
66 FE
65 ABCD
64 BOTM
63 PEAK
50
D2
49
D0
48
D1
47
XWE
46
XRAS
45
A09
44
XCAS
43
XOE
42
DVSS
41
A11
40
A08
39
A07
38
A06
37
A05
36
A04
35
A10
34
A00
33
A01
32
A02
31
A03
30
DVDD
28
XBCK
29
FS256
26
DADT
27
LRCK
24
XBCKI
25
ADDT
23
LRCKI
22
DATAI
21
DOUT
20
DIN1
19
DIN0
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
CONTROL
SPINDLE
SERVO
EACH
BLOCK
BLOCK
EACH
BLOCK
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
APC
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC/ATRAC3
ENCODER/DECODER
DRAM
ADIP
DEMODULATOR/
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA
–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
IC151 CXD2662R (BD (MD) BOARD)
IC141 BH6511FS (BD (MD) BOARD)
91
2
3
1
5
OPIN2 +
6
OPIN2 –
7
OPOUT2
8
GND
9
STBY1
4
BIAS IN
OPIN1 +
OPIN1 –
OPOUT1
11
12
13
14
10
PowVcc1
VO2 (–)
VO2 (+)
VO1 (–)
VO1 (+)
OPIN3 +
OPIN3 –
OPOUT3
GND
STBY2
PreVcc
OPIN4 +
OPIN4 –
OPOUT4
PowVcc2
VO3 (–)
VO3 (+)
VO4 (–)
VO4 (+)
Vcc
STAND BY
CH1 2 3
Level
Shift
Level
Shift
Level
Shift
Vcc
STAND BY
CH4
Vcc
Level
Shift
27
26
28
24
23
22
21
20
25
18
17
16
15
19
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
20k
10k
10k
10k
10k
10k
10k
10k
10k
10k
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP RF_EQ_AMP
ERROR AMP
FOCUS
FOCUS
TRACKING
ERROR AMP
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFO
RFE
FE
TE
(50%/30%
OFF)
OFF)
APC PD AMP
APC LD AMP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
On/Off
CONT2
CONT3
GND
HPFC
VREF
L-IN
R-IN
R-OUT
L-OUT
Vcc
NC
LPFC
ACG
GUR
GLR
ANALOG
SURROUND
VREF
+
+
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
IC102 BA5982FM (BD (CD) BOARD)
IC103 CXA2568M-T (BD (CD) BOARD)
IC202 LA2615 (MAIN BOARD)
IC502 M62016L (MAIN BOARD)
92
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
1
2
3
4
6
VINL
VREF
VINR
VREF(N)
VREF(P)
SFOR
PWON
SYSCLK
5
15
14
10
9
DATAO
WS
FSEL
VSSA
VDDA
BCK
VSSD
VDDD
16
13
12
11
ADC
(Σ∆)
ADC
(Σ∆)
DECIMATION
FILTER
DIGITAL
INTERFACE
CLOCK
CONTROL
7
8
DC-CANCELLATION
FILTER
1
2
3
4
6
7
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15
16 17 18 19
20 21 22
44 43 42
41 40 39 38 37 36 35
34
RESET
RTCB
VDDD
PREEMO
NC
NC
NC
TEST2
WSO
SELSTATIC
TEST1
DATAO
VDDD(C)
VSSD
VSSD(C)
L3DATA
L3CLOCK
DATAI
BCKI
WSI
BCKO
VDDA(PLL)
MUTE
SELCHAN
NC
SPDIF0
VOUTL
SELCLK
SELSPDIF
LOCK
VOUTR
V
DDA(DAC)
SPDIF1
VSSA(PLL)
PREEM1
CLKOUT
NC
VDDA
VSSA
VSSA(DAC)
VREF
TC
L3MODE
NC
L3
INTERFACE
DATA
OUTPUT
INTERFACE
IEC 958
DECODER
AUDIO FEATURE PROCESSOR
INTERPOLATOR
NOISE SHAPER
DAC
DAC
DATA
INPUT
INTERFACE
CLOCK
AND
TIMING CIRCUIT
5
8
9
10
IC1004 LB1641 (DIGITAL BOARD)
IC1005 µDA1360TS (DIGITAL BOARD)
IC1006 µDA1350AH (DIGITAL BOARD)
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