Sony HCD-SR1 / HCD-SR2 / HCD-SR3 (serv.man2) Service Manual ▷ View online
37
HCD-SR1/SR2/SR3
DMB08 BOARD IC607 CXD9618BQ (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
FS2
I
Sampling frequency selection signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.6V)
6
FS1
I
Sampling frequency selection signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock signal input terminal (13.5 MHz)
10
VDDI
—
Power supply terminal (+2.6V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock signal output terminal (13.5 MHz)
13
MS
I
Master/slave selection signal input terminal
“L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the D/A converter and stream processor
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital audio processor
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital audio processor
18
SDI1
I
Front L-ch and R-ch audio serial data input from the digital audio processor
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream
processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter and stream processor
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal (11.2896 MHz) input from the digital audio processor
23
SDO1
O
Front L-ch and R-ch audio serial data output to the stream processor
24
SDO2
O
Center and woofer audio serial data output to the stream processor
25
SDO3
O
Rear L-ch and R-ch audio serial data output to the stream processor
26
SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter
30
SDI2
I
Center and woofer audio serial data input from the digital audio processor
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
SDCLK
O
Clock signal output terminal Not used
38
CLKEN
O
Clock enable signal output terminal Not used
39
RAS
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.6V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used
43
DQM/OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
38
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
Page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
PLL input frequency selection signal input terminal
“L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal
“L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface IC
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream
processor
68
GP9
O
Decode signal output to the system controller
69
GP8
I
Bit 1 input terminal of channel status from the digital audio interface IC
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used
88
XTRST
I
Simple emulation asychronous break input terminal Not used
89
TCK
I
Simple emulation clock signal input terminal Not used
90
TDI
I
Simple emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL reset signal input from the system controller “L”: reset
39
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
114
SDI3
I
Rear L-ch and R-ch audio serial data input from the digital audio processor
115
SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.6V)
40
HCD-SR1/SR2/SR3
DMB08 BOARD IC701 TMC57929PGF-RDP (DVD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the mechanism controller
3
VSS
—
Ground terminal (digital system)
4
D7
I/O
Two-way data bus with the mechanism controller
5
A0
I
Address signal input from the mechanism controller
6
VDD
—
Power supply terminal (+3.3V) (digital system)
7
A1
I
Address signal input from the mechanism controller
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the mechanism controller
15
VSS
—
Ground terminal (digital system)
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the mechanism controller
18
XWR
I
Write strobe signal input from the mechanism controller
19
XCS
I
Chip select signal input from the mechanism controller
20, 21
XINT0, XINT1
O
Interrupt signal output to the mechanism controller
22
VDD
—
Power supply terminal (+3.3V) (digital system)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DSD decoder and DVD system processor
25
VSS
—
Ground terminal (digital system)
26
HDB8
O
Error flag signal output to the DSD decoder and DVD system processor
27
HDB6
O
Stream data signal output to the DSD decoder and DVD system processor
28
VDDS
—
Power supply terminal (+5V) (digital system)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DSD decoder and DVD system processor
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DSD decoder and DVD system processor
33
VSS
—
Ground terminal (digital system)
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DSD decoder and DVD system processor
36
VDD
—
Power supply terminal (+3.3V) (digital system)
37
HDBC
O
Not used
38
VDDS
—
Power supply terminal (+5V) (digital system)
39
HDB2
O
Stream data signal output to the DSD decoder and DVD system processor
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DSD decoder and DVD system processor
42
VSS
—
Ground terminal (digital system)
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DSD decoder and DVD system processor
45
HDBF
O
Not used
46
XDRQ
O
Serial data effect flag signal output to the DSD decoder and DVD system
processor
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XHWR
O
Serial data transfer clock signal output to the DSD decoder and DVD system
processor
49
XHRD
O
Header flag signal output to the DSD decoder
50
VDD
—
Power supply terminal (+3.3V) (digital system)
51
REDY
O
Not used
52
VSS
—
Ground terminal (digital system)
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