Sony HCD-SR1 / HCD-SR2 / HCD-SR3 (serv.man2) Service Manual ▷ View online
41
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
53
XHAC
I
DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground terminal (digital system)
91
MA9
O
Address signal output to the D-RAM
92
MNT1
O
EEPROM ready signal output to the mechanism controller
93
MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD
decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply terminal (+5V)
104 to 106
MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the mechanism controller
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
42
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
117
RFIN
I
RF signal input from the DVD/CD RF amplifier
118, 119
VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123
GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129
VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134
GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor control signal output
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V) (digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DFCT
I
Defect signal input terminal Not used
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the digital signal
processor
147
EXCK
O
Subcode serial data reading clock signal output to the digital signal processor
148
SBIN
I
Subcode serial data input from the digital signal processor
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Sucode sync (S0+S1) detection signal input from the digital signal processor
151
WFCK
I
Write frame clock signal input from the digital signal processor
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used
154
VDDS
—
Power supply terminal (+5V) (digital system)
155
C2PO
I
C2 pointer signal input from the digital signal processor
156
VDD
—
Power supply terminal (+3.3V) (digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
159
DDAT
O
PCM data output terminal Not used
160
MDAT
I
Serial data input from the digital signal processor
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal Not used
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
164
XRST
I
Reset signal input from the mechanism controller “L”: reset
165
IFS0
I
Interface selection signal input terminal Fixed at “L” in this set
166
IFS1
I
Interface selection signal input terminal Fixed at “H” in this set
43
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTL2
O
System clock output terminal (33.8688 MHz)
170
XTL1
I
System clock input terminal (33.8688 MHz)
171
VDD
—
Power supply terminal (+3.3V) (digital system)
172 to 176
D0 to D4
I/O
Two-way data bus with the mechanism controller
44
HCD-SR1/SR2/SR3
DMB08 BOARD IC801 CXD2753R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSCA0
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the mechanism controller
3
MSCK
I
Serial data transfer clock signal input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used
9
XRST
I
Reset signal input from the mechanism controller “L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller
“H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input
12
VSIOA0
—
Ground terminal (for I/O)
13
EXCKO1
O
Master clock signal (33.8688 MHz) output to the digital audio processor
14
EXCKO2
O
External clock 2 signal output terminal Not used
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal Not used
16
F75HZ
O
Not used
17
VDIOA0
—
Power supply terminal (+3.3V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output terminal Not used
26
TCK
I
Clock signal input from the DVD system processor
27
TDI
I
Serial data input from the DVD system processor
28
VSCA1
—
Ground terminal (for core)
29
TDO
O
Serial data output to the DVD system processor
30
TMS
I
TMS signal input from the DVD system processor
31
TRST
I
Reset signal input from the DVD system processor “L”: reset
32 to 34
TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDCA1
—
Power supply terminal (+2.5V) (for core)
36
UBIT
O
Not used
37
XBIT
O
Not used
38 to 41
SUPDT0 to SUPDT3
O
Supplementary data output terminal Not used
42
VSIOA1
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45
VDIOA1
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48
SUPEN
O
Supplementary data enable signal output terminal Not used
49
VSCA2
—
Ground terminal (for core)
50
NC
O
Not used
51, 52
TEST4, TEST5
I
Input terminal for the test (normally: fixed at “L”)
53
NC
O
Not used
54
VDCA2
—
Power supply terminal (+2.5V) (for core)
55, 56
NC
O
Not used
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for
DSD data output “L”: input (slave), “H”: output (master) Fixed at “H” in this set
58
VSDSD0
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output
61
PHREFI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
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