Sony HCD-SR1 / HCD-SR2 / HCD-SR3 (serv.man2) Service Manual ▷ View online
45
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
62
PHREFO
O
Bit clock signal (2.8224 MHz) output to the digital audio processor Not used
63
ZDFL
O
Front L-ch Zero data flag detection signal output terminal Not used
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output terminal Not used
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
67
VDDSD0
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output terminal Not used
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSCB0
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIOB0
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface
Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip
interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip
interface Not used
90
VDIOB0
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface Not used
93
IBCK
O
Data transmission clock signal output terminal for IEEE 1394 link chip interface
Not used
94
VSCB1
—
Ground terminal (for core)
95
IERR
I
Not used
96
IANCI
I
Not used
97
IPLAN
I
Not used
98
IHOLD
O
Not used
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105
IDIN0 to IDIN4
I
Not used
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
IDIN5 to IDIN7
I
Not used
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114
WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for the test (normally: fixed at “L”)
116
VSCB2
—
Ground terminal (for core)
46
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
117 to 120
WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
122
WRFD
I
Not used
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the DVD
decoder
124, 125
WAVDD0, WAVDD1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the DVD/CD
RF amplifier
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS0, WAVSS1
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIO
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the SD-RAM
135
VDIOA2
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
DQ3 to DQ0
I/O
Two-way data bus with the SD-RAM
140
VSIOA3
—
Ground terminal (for I/O)
141
DCLK
O
Clock signal output to the SD-RAM
142
DCKE
O
Clock enable signal output to the SD-RAM
143
XWE
O
Write enable signal output to the SD-RAM
144
XCAS
O
Column address strobe signal output to the SD-RAM
145
XRAS
O
Row address strobe signal output to the SD-RAM
146
VDIOA3
—
Power supply terminal (+3.3V) (for I/O)
147
NC
O
Not used
148, 149
A11, A10
O
Address signal output to the SD-RAM
150
VSCA3
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the SD-RAM
153
VDCA3
—
Power supply terminal (+2.5V) (for core)
154 to 157
A7 to A4
O
Address signal output to the SD-RAM
158
VSIOA4
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the SD-RAM
163
VDIOA4
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the DVD decoder
165
XSHD
I
Header flag signal input from the DVD decoder
166
SDCK
I
Serial data transfer clock signal input from the DVD decoder
167
XSAK
I
Serial data effect flag signal input from the DVD decoder
168
SDEF
I
Error flag signal input from the DVD decoder
169 to 176
SD0 to SD7
I
Stream data signal input from the DVD decoder
47
HCD-SR1/SR2/SR3
DMB08 BOARD IC901 uPD703033BYGF-M59-3BA-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP-DATA
O
Serial data output to the stream processors
2
DAMP-CLK
O
Serial data transfer clock signal output to the stream processors
3
I2C-DATA
I/O
Communication data bus with the DVD system processor and mechanism
controller
4
CQ-RST
O
Reset signal output to the DVD system processor “L”: reset
5
I2C-CLK
I/O
Communication data reading clock signal input or transfer clock signal output
with the DVD system processor and mechanism controller
6
DSP-DO
I
Write data input from the audio digital signal processor
7
DIG-DI
O
Read data output to the digital audio interface IC, audio digital signal processor
and D/A converter
8
DIG-CLK
O
Clock signal output to the digital audio interface IC, audio digital signal processor
and D/A converter
9
EVDD
—
Power supply terminal (+5V)
10
EVSS
—
Ground terminal
11
P-PWM
O
PWM voltage control signal output
12
DSP-RST
O
Reset signal output to the audio digital signal processor “L”: reset
13
DSP-PM
O
PLL reset signal output to the audio digital signal processor “L”: reset
14
DSP-CS
O
Chip select signal output to the audio digital signal processor
15
DSP-HACN
I
Acknowledge signal input from to the audio digital signal processor
16
DSP-BST
O
Boot strap signal output to the audio digital signal processor
17
DSP-GP9
I
Decode signal input from to the audio digital signal processor
18
DIR-ZERO
I
Audio serial data input from the digital audio interface IC
19
DIR-ERR
I
PLL lock error and data error flag input from the digital audio interface IC
20
DIR-CE
O
Chip enable signal output to the digital audio interface IC
21
VPP
—
Power supply terminal (for programming) Not used
22
DIR-XST
I
Source clock switching monitor input from the digital audio interface IC
23
DIR-AD
O
Muting signal output
24
DIR-XMODE
O
System reset signal output to the digital audio interface IC “L”: reset
25
DIRDO
I
Write data input from the digital audio interface IC
26
DAMP-RST
O
Reset signal output to the stream processors “L”: reset
27
GP12
—
Not used (fixed at “L”)
28
DAMP-MUTEN
O
Muting on/off control signal output to the stream processors “H”: muting on
29
CS1
O
Chip select signal output to the stream processor (for front L-ch and R-ch)
30
CS2
O
Chip select signal output to the stream processor (for center and woofer)
31
CS3
O
Chip select signal output to the stream processor (for rear L-ch and R-ch)
32
DAC-CS
O
Chip select signal output to the D/A converter
33
AD-RST
O
Reset signal output to the A/D converter and D/A converter “L”: reset
System reset signal input “L”: reset
34
RESET
I
For several hundreds msec. after the power supply rises, “L” is input, then it
changes to “H”
35
XT1
I
Sub system clock input terminal Not used (open)
36
XT2
O
Sub system clock output terminal Not used (open)
37
REGC
—
Capacitance connection terminal
38
X2
O
Main system clock output terminal (20 MHz)
39
X1
I
Main system clock input terminal (20 MHz)
40
VSS
—
Ground terminal
41
VDD
—
Power supply terminal (+5V)
48
HCD-SR1/SR2/SR3
Pin No.
Pin Name
I/O
Description
42
CLKOUT
O
Clock signal output terminal Not used (open)
43
DIP-RST
O
Reset signal output to the power drivers “L”: reset
44
DIP-OCP
I
Protect signal input from the over load detection circuit
45
ST-POWER
O
System power on/off control signal output “H”: power on
46
HP-MUTE
O
Headphone muting on/off control signal output “L”: muting on
47
AU-MUTE
O
Audio line muting on/off control signal output “L”: muting on
48
VIDEO-MUTE
O
Video muting signal output
49
PROG SW
I
SCAN SELECT switch input terminal “L”: SELECTABLE, “H”: INTERLACE
50
FM750
O
Power supply for tuner pack on/off control signal output
51
TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
52
TUN-DI
I
Serial data input from the tuner unit
53
TUN-CE
O
Chip enable signal output to the tuner unit
54
TUN-DO
O
Serial data output to the tuner unit
55
TUN-CLK
O
Serial data transfer clock signal output to the tuner unit
56
FL-MUTE
O
Reset signal output to the fluorescent indicator tube driver “L”: reset
57
FL-CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
58
BVDD
—
Power supply terminal (+5V) (for bus interface)
59
BVSS
—
Ground terminal (for bus interface)
60
FL-DATA
O
Serial data output to the fluorescent indicator tube driver
61
FL-CS
O
Chip select signal output to the fluorescent indicator tube driver “L” active
62
LED-CS
—
Not used
63
LED-CLR
—
Not used
64
HPSW
I
Connection detection signal input of the headphone jack “L”: no connection,
“H”: headphone connected
65
DF-RST
O
Reset signal output to the digital audio processor “L”: reset
66
PCON3
O
Standby LED control signal output
67
SW2
I
Chucking detection switch signal input
68
F-IN
O
Motor drive signal output
69
R-IN
O
Motor drive signal output
70
DVD_SEL
O
DVD select signal output
71, 72
NC
—
Not used
73
RGB_SEL
O
RGB select signal output
74
AVDD
—
Power supply terminal (+5V) (analog system)
75
AVSS
—
Ground terminal (analog system)
76
AVREF
—
Reference voltage (+5V) input terminal (analog system)
77
NC
—
Not used (fixed at “L”)
78
SW1
I
Loading out detection switch signal input
79
SW3
I
Trigger detection switch signal input
80
AREA1
I
Destination setting terminal
81
SEN2
I
Disc loading detection signal input
82 to 84
KEY0 to KEY2
I
Key input terminal (A/D input)
85, 86
NC
—
Not used (fixed at “L”)
87
MODEL
I
Model setting terminal
88
RDS-DATA
I
RDS serial data input from the RDS decoder
89
DVD-POWER
O
DVD power on/off control signal output “H”: power on
90
STOP
I
System power stop signal input
91
POWER-SW
I
AC power detection signal input
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