Sony HCD-LF10 Service Manual ▷ View online
78
HCD-LF10
Pin No.
Pin Name
I/O
Description
120
VCOR1
-
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123
GNDA4, GNDA3
-
Ground terminal
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129
VCCA3, VCCA2
-
Power supply terminal (+3.3V)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134
GNDA2, GNDA1
-
Ground terminal
135
SPO
O
Spindle motor control signal output terminal
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor servo drive signal input terminal
138
MDIN1
I
MDP input terminal
139
VCCA1
-
Power supply terminal (+3.3V)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
-
Ground terminal
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
-
Power supply terminal (+3.3V)
144
MDPOUT
O
Phase error output of internal CLV circuit
145
DFCT
I
Defect signal input from the DSP
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the DSP
147
EXCK
O
Subcode serial data reading clock signal output to the DSP
148
SBIN
I
Subcode serial data input from the DSP
149
VSS
-
Ground terminal
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
151
WFCK
I
Write frame clock signal input from the DSP
152
VDD5V
-
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used
154
VDDS
-
Power supply terminal (+5V)
155
C2PO
I
C2 pointer signal input from the DSP
156
VDD
-
Power supply terminal (+3.3V)
157
DBCK
O
Bit clock signal output terminal Not used
158
BCLK
I
Bit clock signal input from the DSP
159
DDAT
O
PCM data output terminal Not used
160
MDAT
I
Serial data input from the DSP
161
VSS
-
Ground terminal
162
DLRC
O
L/R sampling clock signal output terminal Not used
163
LRCK
I
L/R sampling clock signal input from the DSP
164
XRST
I
Reset signal input from the mechanism controller "L": reset
165
IFS0
I
Interface selection signal input terminal Fixed at "L" in this set
166
IFS1
I
Interface selection signal input terminal Fixed at "H" in this set
167
XTAL
I
System clock (33.8688 MHz) input terminal
168
VSS
-
Ground terminal
169
XTL2
O
System clock (33.8688 MHz) output terminal
170
XTL1
I
System clock (33.8688 MHz) input from the clock generator
79
HCD-LF10
Pin No.
Pin Name
I/O
Description
171
VDD
-
Power supply terminal (+3.3V)
172 to 176
D0 to D4
I/O
Two-way data bus with the mechanism controller
80
HCD-LF10
DMB07 BOARD IC801 CXD2753R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSCA0
-
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the mechanism controller
3
MSCK
I
Serial data transfer clock signal input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
-
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller "L": ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used
9
XRST
I
Reset signal input from the mechanism controller "L": reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller "H": muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input from the clock generator
12
VSIOA0
-
Ground terminal (for I/O)
13
ECCKO1
O
Master clock signal (22.5792 MHz) output to the digital audio processor
14
EXCKO2
O
External clock signal output terminal Not used
15
LRCK
O
L/R sampling clock signal output terminal Not used
16
F75HZ
O
Not used
17
VDIOA0
-
Power supply terminal (+3.3V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output terminal Not used
26
TCK
I
Clock signal input terminal (for JTAG)
27
TDI
I
Serial data input terminal (for JTAG)
28
VSCA1
-
Ground terminal (for core)
29
TDO
O
Serial data output terminal (for JTAG)
30
TMS
I
Mode selection signal input terminal (for JTAG)
31
TRST
I
Reset signal input terminal (for JTAG)
32 to 34
TEST1 to TEST3
I
Input terminal for the test (normally: fixed at "L")
35
VDCA1
-
Power supply terminal (+2.5V) (for core)
36
UBIT
O
Monitor terminal relative to DST Not used
37
XBIT
O
Monitor terminal relative to DST Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used
42
VSIOA1
-
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45
VDIOA1
-
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48
SUPEN
O
Supplementary data enable signal output terminal Not used
49
VSCA2
-
Ground terminal (for core)
50
NC
O
Not used
51, 52
TESTI
I
Input terminal for the test (normally: fixed at "L")
53
NC
O
Not used
54
VDCA2
-
Power supply terminal (+2.5V) (for core)
55
DSADML
O
DSD data output terminal for L-ch down mix Not used
56
DSADMR
O
DSD data output terminal for R-ch down mix Not used
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal for DSD data output
"L": input (slave), "H": output (master) Fixed at "H" in this set
"L": input (slave), "H": output (master) Fixed at "H" in this set
58
VSDSD0
-
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal input terminal for DSD data output Not used
81
HCD-LF10
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal output for DSD data output to the digital audio processor
61
PHREFI
I
Phase reference signal input terminal for DSD output phase modulation Not used
62
PHREFO
O
Phase reference signal output terminal for DSD output phase modulation Not used
63
ZDFL
O
Zero data flag (for front L-ch) detection signal output terminal Not used
64
DSAL
O
DSD data (for front L-ch) output to the digital audio processor
65
ZDFR
O
Zero data flag (for front R-ch) detection signal output terminal Not used
66
DSAR
O
DSD data (for front R-ch) output to the digital audio processor
67
VDDSD0
-
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Zero data flag (for center) detection signal output terminal Not used
69
DSAC
O
DSD data (for center) output to the digital audio processor
70
ZDFLFE
O
Zero data (for sub woofer) flag detection signal output terminal Not used
71
DSALFE
O
DSD data (for sub woofer) output to the digital audio processor
72
VSDSD1
-
Ground terminal (for DSD data output)
73
ZDFLS
O
Zero data flag (for rear L-ch) detection signal output terminal Not used
74
DSALS
O
DSD data (for rear L-ch) output to the digital audio processor
75
ZDFRS
O
Zero data flag (for rear R-ch) detection signal output terminal Not used
76
DSARS
O
DSD data (for rear R-ch) output to the digital audio processor
77
VDDSD1
-
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
I/O
Two-way data bus terminal Not used
80
VSCB0
-
Ground terminal (for core)
81, 82
IOUT2, IOUT3
I/O
Two-way data bus terminal Not used
83
VDCB0
-
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
I/O
Two-way data bus terminal Not used
86
VSIOB0
-
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal Not used
88
IFULL
I
Data transmission hold request signal input terminal Not used
89
IEMPTY
I
High speed transmission request signal input terminal Not used
90
VDIOB0
-
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal Not used
92
IOUTE
O
Enable signal output terminal Not used
93
IBCK
O
Data transmission clock signal output terminal Not used
94
VSCB1
-
Ground terminal (for core)
95
IERR
I
Not used
96
IANCI
I
Not used
97
IPLAN
I
Not used
98
IHOLD
O
Not used
99
VDCB1
-
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105 IDIN0 to IDIN4
I
Not used
106
VSIOB1
-
Ground terminal (for I/O)
107 to 109 IDIN5 to IDIN7
I
Not used
110
VDIOB1
-
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for disc inspection mode from the mechanism controller
116
VSCB2
-
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDCB2
-
Power supply terminal (+2.5V) (for core)
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