Sony HCD-LF10 Service Manual ▷ View online
74
HCD-LF10
Pin No.
Pin Name
I/O
Description
144
AVSS1
-
Ground terminal
145
VDD
-
Power supply terminal (+1.8V)
146
GND
-
Ground terminal
147
XCK
O
Audio system clock output to the digital audio processor
148
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital audio processor
149
BCK
O
Bit clock signal (2.8224 MHz) output to the digital audio processor
150
DATA0 (DM)
O
Audio data (for down mix) output to the D/A converter
151
DATA1 (FLR)
O
Audio data (for front) output to the digital audio processor
152
VDDP
-
Power supply terminal (+3.3V)
153
GNDP
-
Ground terminal
154
DATA2 (SLR)
O
Audio data (for surround (rear)) output to the digital audio processor
155
DATA3 (CSW)
O
Audio data (for center and sub woofer) output to the digital audio processor
156
IEC958
O
S/PDIF signal output terminal Not used
157
DAI_DATA
I
Data input terminal Not used
158
DAI_BCK
I
Bit clock signal input terminal Not used
159
DAI_LRCK
I
L/R sampling clock signal input terminal Not used
160
I2C_CL
I/O
Two-way I2C clock bus with the system controller and mechanism controller
161
I2C_DA
I/O
Two-way I2C data bus with the system controller and mechanism controller
162
CS (ZIVA_E2P)
O
Chip select signal output to the EEPROM
163
RXD1
I
Serial data input terminal for check jig
164
TXD1
O
Serial data output terminal for check jig
165
WRITE_CTRL
(ZIVA_E2P)
O
Write control signal output to the EEPROM
166
GNDP
-
Ground terminal
167
VDDP
-
Power supply terminal (+3.3V)
168 to 171
SDDATA7 to
SDDATA4
I
Stream data signal input from the DVD decoder
172
GND
-
Ground terminal
173
VDD
-
Power supply terminal (+1.8V)
174 to 177
SDDATA3 to
SDDATA0
I
Stream data signal input from the DVD decoder
178
SDREQ
O
Serial data request signal output to the DVD decoder
179
SDEN
I
Serial data enable signal input from the DVD decoder
180
GNDP
-
Ground terminal
181
VDDP
-
Power supply terminal
182
SDERROR
I
Serial data error flag signal input from the DVD decoder
183
SDCLK
I
Serial data transfer clock signal input from the DVD decoder
184
HIRQ1
I
Interrupt request signal input from the mechanism controller
185
DRVCLK
I
Serial data transfer clock signal input from the mechanism controller
186
DRVTX
I
Serial data input from the EEPROM and mechanism controller
187
DRVRX
O
Serial data output to the EEPROM and mechanism controller
188
DRVRDY
I
Ready signal input from the mechanism controller
189
VNW
-
Power supply terminal (+5V)
190
ALE
O
Latch enable signal output to the address latch
191
RST_SPC
O
Reset signal output to the mechanism controller "L": reset
192
INT/EXT
O
Internal/external selection signal output terminal
193, 194
HCS2, HCS1
O
Chip select signal output terminal Not used
195
HCS0
O
Chip select signal output to the programmable ROM
75
HCD-LF10
Pin No.
Pin Name
I/O
Description
196
VDDP
-
Power supply terminal (+3.3V)
197
TRST
I
Reset signal input terminal (for JTAG)
198
TDO
O
Data output terminal (for JTAG)
199
TDI
I
Data input terminal (for JTAG)
200
TMS
I
Mode selection signal input terminal (for JTAG)
201
TCK
I
Clock signal input terminal (for JTAG)
202
RESET
I
Reset signal input from the system controller "L": reset
203
BUS CLK
O
Not used
204
GND
-
Ground terminal
205
VDD
-
Power supply terminal (+1.8V)
206
HA3
O
Address signal output to the programmable ROM
207
HA2
O
Address signal output to the programmable ROM and address latch
208
GNDP
-
Ground terminal
76
HCD-LF10
DMB07 BOARD IC701 TMC57929PGF-RDP (DVD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the mechanism controller
3
VSS
-
Ground terminal
4
D7
I/O
Two-way data bus with the mechanism controller
5
A0
I
Address signal input from the mechanism controller
6
VDD
-
Power supply terminal (+3.3V)
7
A1
I
Address signal input from the mechanism controller
8
VDD5V
-
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the mechanism controller
15
VSS
-
Ground terminal
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the mechanism controller
18
XWR
I
Write strobe signal input from the mechanism controller
19
XCS
I
Chip select signal input from the mechanism controller
20, 21
XINT0, XINT1
O
Interrupt signal output to the mechanism controller
22
VDD
-
Power supply terminal (+3.3V)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DVD system processor and DSD decoder
25
VSS
-
Ground terminal
26
SDEF
O
Serial data error flag signal output to the DVD system processor and DSD decoder
27
HDB6
O
Stream data signal output to the DVD system processor and DSD decoder
28
VDDS
-
Power supply terminal (+5V)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DVD system processor and DSD decoder
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DVD system processor and DSD decoder
33
VSS
-
Ground terminal
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DVD system processor and DSD decoder
36
VDD
-
Power supply terminal (+3.3V)
37
HDBC
O
Not used
38
VDDS
-
Power supply terminal (+5V)
39
HDB2
O
Stream data signal output to the DVD system processor and DSD decoder
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DVD system processor and DSD decoder
42
VSS
-
Ground terminal
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DVD system processor and DSD decoder
45
HDBF
O
Not used
46
HDRQ
O
Serial data effect flag signal output to the DVD system processor and DSD decoder
47
VDDS
-
Power supply terminal (+5V)
48
XHWR
O
Serial data transfer clock signal output to the DVD system processor and DSD decoder
49
XHRD
O
Header flag signal output to the DSD decoder
50
VDD
-
Power supply terminal (+3.3V)
51
REDY
O
Not used
52
VSS
-
Ground terminal
53
XHAC
I
Serial data request signal input from the DVD system processor and DSD decoder
77
HCD-LF10
Pin No.
Pin Name
I/O
Description
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
-
Power supply terminal (+5V)
59, 60
HA0, HA2
I
Not used
61
VSS
-
Ground terminal
62, 63
HCS0, HCS1
I
Not used
64
VDD
-
Power supply terminal (+3.3V)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
-
Ground terminal
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
-
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
-
Power supply terminal (+3.3V)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
-
Ground terminal
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
-
Power supply terminal (+3.3V)
89
MA8
O
Address signal output to the D-RAM
90
VSS
-
Ground terminal
91
MA9
O
Address signal output to the D-RAM
92
MNT1
O
EEPROM ready signal output to the mechanism controller
93
MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
-
Ground terminal
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
-
Power supply terminal (+3.3V)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
-
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the mechanism controller
108
VSS
-
Ground terminal
109
APE0
O
Absolute phase error signal output terminal
110
VDD
-
Power supply terminal (+3.3V)
111
DASYO
O
RF binary signal output terminal
112
GNDA5
-
Ground terminal
113, 114
ASF1, AFS2
-
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
117
RFIN
I
RF signal input from the CD/DVD/SACD RF amplifier
118, 119
VCCA5, VCCA4
-
Power supply terminal (+3.3V)
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