Sony HCD-LF10 Service Manual ▷ View online
70
HCD-LF10
– DRIVER Board –
IC701
BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
– DVD POWER Board –
IC901
SI-8120JF
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
ON/OFF
SOFT
START
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
ON/OFF
IC902
SI-8050S-LF1101
IC903
SI-8033S
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
S.S
71
HCD-LF10
– I/O Board –
IC201
MM1623BFBE
1
VCC1
2
C IN
3
MUTE 1
4
CVBS IN
28 VCC2
23 CVBS OUT
25 S1
150k
Ω
BIAS
12
CB IN
150k
Ω
BIAS
CLAMP
6dB
6dB
6
Y IN
7
GND
8
BIAS
CLAMP
BIAS
6dB
9
I/P
10
CY IN
11
CLP
13
MUTE2
5
YC MIX
+
6dB
–6dB
6dB
27 S-DC OUT
24 S2
LOW-PASS
FILTER
21 Y OUT
22 GND2
6.75MHz
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
20 CY OUT
75
Ω
DRIVER
S-DC OUT
S1/S2
26 C OUT
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
CLAMP
150k
Ω
BIAS
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
18 CB OUT
19 GND2
17 GND2
15 GND2
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
14
CR IN
150k
Ω
BIAS
16 CR OUT
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
6dB
6dB
– TOUCH KEY Board –
IC402
TK11145CSCL-G
1
2
3
5
4
VCONT
GND
NP
VIN
VOUT
CONTROL
CIRCUIT
OVER HEAT &
OVER CURRENT
PROTECTION
BANDGAP
REFERENCE
72
HCD-LF10
•
IC Pin Function Description
DMB07 BOARD IC207 ZIVA5X-C2F-B (DVD SYSTEM PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDDP
-
Power supply terminal (+3.3V)
2
HA1
O
Address signal output to the programmable ROM and address latch
3 to 11
HD15 to HD7
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
12
VDDP
-
Power supply terminal (+3.3V)
13
GNDP
-
Ground terminal
14 to 19
HD6 to HD1
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
20
VDDP
-
Power supply terminal (+3.3V)
21
GNDP
-
Ground terminal
22
HD0
I/O
Two-way data bus (address signal multiplexed) with the programmable ROM and address latch
23
HDTACK
I
Acknowledge signal input terminal for host data transfer Not used
24
HIRQ0
I
Interrupt signal input terminal Not used
25
WEH.UDS
O
Write enable host upper data strobe signal output to the programmable ROM
26
WEL.LDS
O
Write enable host lower data strobe signal output terminal Not used
27
HREAD
O
Output enable signal output to the programmable ROM
28
GPIO0
I
Check jig detection signal input terminal
29
GND
-
Ground terminal
30
VDD
-
Power supply terminal (+1.8V)
31
GND25
-
Ground terminal
32
VDD25
-
Power supply terminal (+3.3V)
33 to 42
MA9 to MA0
O
Address signal output to the SD-RAM
43
GND25
-
Ground terminal
44
VDD25
-
Power supply terminal (+3.3V)
45, 46
MA10,MA11
O
Address signal output to the SD-RAM
47, 48
BA1, BA0
O
Bank select signal output to the SD-RAM
49
MCS0
O
Chip select signal output to the SD-RAM
50
MCS1
O
Chip select signal output terminal Not used
51
MRAS
O
Row address strobe signal output to the SD-RAM
52
MCAS
O
Column address strobe signal output to the SD-RAM
53
MWE
O
Write enable signal output to the SD-RAM
54
GND25
-
Ground terminal
55
VDD25
-
Power supply terminal (+3.3V)
56
MCLK
O
Master clock signal output to the SD-RAM
57 to 60
MD0 to MD3
I/O
Two-way data bus with the SD-RAM
61
GND25
-
Ground terminal
62
MDQM0
O
Write mask signal output to the SD-RAM
63
VDD25
-
Power supply terminal (+3.3V)
64 to 71
MD6 to MD11
I/O
Two-way data bus with the SD-RAM
72
GND25
-
Ground terminal
73
MDQM1
O
Write mask signal output to the SD-RAM
74
VDD25
-
Power supply terminal (+3.3V)
75 to 78
MD12 to MD15
I/O
Two-way data bus with the SD-RAM
79
GND
-
Ground terminal
80
VDD
-
Power supply terminal (+1.8V)
81 to 84
MD16 to MD19
I/O
Two-way data bus with the SD-RAM
85
GND25
-
Ground terminal
86
MDQM2
O
Write mask signal output to the SD-RAM
73
HCD-LF10
Pin No.
Pin Name
I/O
Description
87
VDD25
-
Power supply terminal (+3.3V)
88 to 95
MD20 to MD27
I/O
Two-way data bus with the SD-RAM
96
GND25
-
Ground terminal
97
MDQM3
O
Write mask signal output to the SD-RAM
98
VDD25
-
Power supply terminal (+3.3V)
99 to 102
MD28 to MD31
I/O
Two-way data bus with the SD-RAM
103
GND25
-
Ground terminal
104
VDD25
-
Power supply terminal (+3.3V)
105
VCLK
O
Not used
106
XCK_I/O_SEL
O
Not used
107
VS
O
Wide control signal output to the system controller
108
I/P SW
O
Interlace/progressive selection signal output to the system controller
"L": interlace, "H": progressive
"L": interlace, "H": progressive
109
CDSEL
O
Digital out signal selection signal output terminal Not used
110
MREQ
O
Muting request signal output to the system controller
111
VDDP
-
Power supply terminal (+3.3V)
112
GNDP
-
Ground terminal
113
MDI
O
Serial data output to the D/A converter
114
MC
O
Serial data transfer clock signal output to the D/A converter
115
ML
O
Serial data latch pulse signal output to the D/A converter
116
HIRQ2
I
Busy signal input from the EEPROM
117
VDAC_4B
-
Ground terminal
118
VDAC_VDD4
-
Power supply terminal (+3.3V)
119
VDAC_4
O
Component video signal output to the video amplifier
120
VDAC_3B
-
Ground terminal
121
VDAC_VDD3
-
Power supply terminal (+3.3V)
122
VDAC_3
O
Component video signal output to the video amplifier
123
VDAC_2B
-
Ground terminal
124
VDAC_VDD2
-
Power supply terminal (+3.3V)
125
VDAC_2
O
Y signal output to the video amplifier
126
VDAC_1B
-
Ground terminal
127
VDAC_VDD1
-
Power supply terminal (+3.3V)
128
VDAC_1
O
Chroma signal output to the video amplifier
129
VDAC_0B
-
Ground terminal
130
VDAC_VDD0
-
Power supply terminal (+3.3V)
131
VDAC_0
O
Video signal output to the video amplifier
132
VDAC_DVSS
-
Ground terminal
133
VDAC_DVDD
-
Power supply terminal (+3.3V)
134
VDAC_REFVDD
-
Power supply terminal (+3.3V)
135
VDAC_REF
I
Reference voltage input terminal
136
VDAC_REFVSS
-
Ground terminal
137
XVSS
-
Ground terminal
138
XOUT
O
Clock signal output terminal Not used
139
XIN
I
System clock signal (27 MHz) input from the clock generator
140
XVDD
-
Power supply terminal (+3.3V)
141
AVSS2
-
Ground terminal
142
AVDD2
-
Power supply terminal (+3.3V)
143
AVDD1
-
Power supply terminal (+3.3V)
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