Sony HCD-FC7 (serv.man2) Service Manual ▷ View online
97
HCD-FC7
Pin No.
Pin Name
I/O
Description
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTL2
O
System clock output terminal (33.8688 MHz)
170
XTL1
I
System clock input terminal (33.8688 MHz)
171
VDD
—
Power supply terminal (+3.3V) (digital system)
172 to 176
D0 to D4
I/O
Two-way data bus with the mechanism controller
98
HCD-FC7
Pin No.
Pin Name
I/O
Description
1
VSCA0
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the mechanism controller
3
MSCK
I
Serial data transfer clock signal input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used
9
XRST
I
Reset signal input from the mechanism controller “L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller “H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input
12
VSIOA0
—
Ground terminal (for I/O)
13
EXCKO1
O
Master clock signal (33.8688 MHz) output to the digital audio processor
14
EXCKO2
O
External clock 2 signal output terminal Not used
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal Not used
16
F75HZ
O
Not used
17
VDIOA0
—
Power supply terminal (+3.3V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output terminal Not used
26
TCK
I
Clock signal input from the DVD system processor
27
TDI
I
Serial data input from the DVD system processor
28
VSCA1
—
Ground terminal (for core)
29
TDO
O
Serial data output to the DVD system processor
30
TMS
I
TMS signal input from the DVD system processor
31
TRST
I
Reset signal input from the DVD system processor “L”: reset
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDCA1
—
Power supply terminal (+2.5V) (for core)
36
UBIT
O
Not used
37
XBIT
O
Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used
42
VSIOA1
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used
45
VDIOA1
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used
48
SUPEN
O
Supplementary data enable signal output terminal Not used
49
VSCA2
—
Ground terminal (for core)
50
NC
O
Not used
51, 52
TEST4, TEST5
I
Input terminal for the test (normally: fixed at “L”)
53
NC
O
Not used
54
VDCA2
—
Power supply terminal (+2.5V) (for core)
55, 56
NC
O
Not used
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data
output “L”: input (slave), “H”: output (master) Fixed at “H” in this set
output “L”: input (slave), “H”: output (master) Fixed at “H” in this set
58
VSDSD0
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output
• DVD BOARD IC801 CXD2753R (DSD DECODER)
99
HCD-FC7
Pin No.
Pin Name
I/O
Description
61
PHREFI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
62
PHREFO
O
Bit clock signal (2.8224 MHz) output to the digital audio processor Not used
63
ZDFL
O
Front L-ch Zero data flag detection signal output terminal Not used
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output terminal Not used
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
67
VDDSD0
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output terminal Not used
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSCB0
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIOB0
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip interface
Not used
Not used
90
VDIOB0
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface Not used
93
IBCK
O
Data transmission clock signal output terminal for IEEE 1394 link chip interface Not used
94
VSCB1
—
Ground terminal (for core)
95
IERR
I
Not used
96
IANCI
I
Not used
97
IPLAN
I
Not used
98
IHOLD
O
Not used
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105
Not used
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
Not used
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for the test (normally: fixed at “L”)
116
VSCB2
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
IDIN0 to IDIN4
IDIN5 to IDIN7
I
I
100
HCD-FC7
Pin No.
Pin Name
I/O
Description
122
WRFD
I
Not used
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the DVD decoder
124, 125
WAVDD0,
WAVDD1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the DVD/CD RF amplifier
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS0, WAVSS1
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIO
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the SD-RAM
135
VDIOA2
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
Two-way data bus with the SD-RAM
140
VSIOA3
—
Ground terminal (for I/O)
141
DCLK
O
Clock signal output to the SD-RAM
142
DCKE
O
Clock enable signal output to the SD-RAM
143
XWE
O
Write enable signal output to the SD-RAM
144
XCAS
O
Column address strobe signal output to the SD-RAM
145
XRAS
O
Row address strobe signal output to the SD-RAM
146
VDIOA3
—
Power supply terminal (+3.3V) (for I/O)
147
NC
O
Not used
148, 149
A11, A10
O
Address signal output to the SD-RAM
150
VSCA3
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the SD-RAM
153
VDCA3
—
Power supply terminal (+2.5V) (for core)
154 to 157
Address signal output to the SD-RAM
158
VSIOA4
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the SD-RAM
163
VDIOA4
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the DVD decoder
165
XSHD
I
Header flag signal input from the DVD decoder
166
SDCK
I
Serial data transfer clock signal input from the DVD decoder
167
XSAK
I
Serial data effect flag signal input from the DVD decoder
168
SDEF
I
Error flag signal input from the DVD decoder
169 to 176
SD0 to SD7
I
Stream data signal input from the DVD decoder
DQ3 to DQ0
I/O
A7 to A4
O
Click on the first or last page to see other HCD-FC7 (serv.man2) service manuals if exist.