Sony HCD-FC7 (serv.man2) Service Manual ▷ View online
85
HCD-FC7
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
I/O
—
—
—
—
—
O
I
I
I
I/O
I/O
O
I
O
O
—
—
I
I
I
I
—
—
I
I
I
I
O
I
—
—
I
I
I
I
I
O
I
—
O
O
O
O
I/O
O
—
I
O
I
I
Pin Name
GPIO4 (2)
VDDP
GNDP
GPIO4 (3)
GPIO4 (4)
IEC958
DAI_DATA
DAI_BCK
DAI_LRCK
I2C_CL
I2C_DA
CS(ZIVA_E2P)
RXD1
TXD1
WRITE_CTRL(ZIVA_E2P)
GNDP
VDDP
SDDATA7
SDDATA6
SDDATA5
SDDATA4
GND
VDD
SDDATA3
SDDATA2
SDDATA1
SDDATA0
SDREQ
SDEN
GNDP
VDDP
SDERROR
SDCLK
HIRQ1
DRVCLK
DRVTX
DRVRX
DRVRDY
VNW
ALE
RST_SPC
HCS3
HCS2
HCS1
HCS0
VDDP
TRST
TDO
TDI
TMS
Description
Not used (pull-up)
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Not used (pull-down)
Not used (pull-down)
S/PDIF signal
Data input from ADC (not used)
BCK signal input from ADC (not used)
LRCK signal input from ADC (not used)
I2C clock bus
I2C data bus
Chip select signal output to the EEPROM (IC203)
Serial data input for check jig
Serial data output for check jig
Write control signal output to the EEPROM (IC203)
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data7 input
SDBus data6 input
SDBus data5 input
SDBus data4 input
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
SDBus data3 input
SDBus data2 input
SDBus data1 input
SDBus data0 input
SDBus data request signal output
SDBus data enable signal input
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data error signal input
SDBus data clock input
Interrupt signal input from the mechanism controller (IC301)
Serial data clock input from the mechanism controller (IC301)
Serial data input from the mechanism controller (IC301) and the EEPROM (IC203)
Serial data output to the mechanism controller (IC301) and the EEPROM (IC203)
Ready signal input from the mechanism controller (IC301)
Power supply for 5V tolerance voltage input
Latch enable signal output for address data demux
Reset signal output to the mechanism controller (IC301)
Not used
Chip select signal output for Medusa (not used)
Not used
Chip select signal output to the external ROM (IC205)
Power supply terminal (+3.3V) (I/O signal)
Reset signal input
Data output
Data input
TMS signal input
86
HCD-FC7
Pin No.
201
202
203
204
205
206
207
208
I/O
I
I
I/O
—
—
I/O
I/O
—
Pin Name
TCK
RESET
BUS CLK
GND
VDD
HA3
HA2
GNDP
Description
TCK signal input
ZIVA reset input
Not used
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
Address bus 3
Address bus 2
Ground terminal (I/O signal)
87
HCD-FC7
Pin No.
Pin Name
I/O
Description
1
EEP SO
O
Not used
2
SDEN
O
Serial data enable signal output to DVD/CD RF amplifier
3
DOCTRL/
ISBTEST
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
XRST DSD
O
Reset signal output to the DSD decoder “L”: reset
5
EEP SI
I/O
Two-way data bus with the EEPROM
6
EEP RDY
I
EEPROM ready signal input from the DVD decoder
7
FCS JMP 1
O
Focus jump 1 signal output to the motor/coil driver
8
FCS JMP 2
O
Focus jump 2 signal output to the motor/coil driver
9
SENS CD
I
Internal status (SENSE) signal input from the digital signal processor
10
CDSP2
O
Clock selection signal output to the digital signal processor
11
CDSP4
Not used
12
XCS DVD
O
Chip select signal output to the DVD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the DVD decoder
22
INIT0 DVD
I
Interrupt signal input from the DVD decoder
23
INIT1 DVD
I
Interrupt signal input from the DVD decoder
24
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder
25
XRST DVD
O
Reset signal output to the DVD decoder “L”: reset
26
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27
LAT CD
O
Serial data latch pulse signal output to the digital signal processor
28
LD ON
O
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
29
MIRR
I
Mirror signal input from the digital signal processor
30
COUT CD
I
Numbers of track counted signal input from the digital signal processor
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS ZIVA
O
Chip select signal output to the DVD system processor
33
SI ZIVA
I
Serial data input from the DVD system processor
34
SO ZIVA
O
Serial data output to the DVD system processor
35
SCK ZIVA
O
Serial data transfer clock signal output to the DVD system processor
36
DRVIRQ
O
Interrupt request signal output to the DVD system processor
37
DRVRDY
O
Ready signal output to the DVD system processor
38
RST
I
System reset signal input from the DVD system processor “L”: reset
39
VSS
—
Ground terminal (digital system)
40
XTAL I
System clock input terminal (20 MHz)
41
EXTAL O
System clock output terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43, 44
SLED A, SLED B
O
Sled motor drive signal output
45
JIT OFFSET
O
Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
46
SDOUT DSD
O
Serial data output to the DSD decoder
47
SDIN DSD
I
Serial data input from the DSD decoder
48
READY DSD
I
Ready signal input from the DSD decoder “L”: ready
49
DATA CD
O
Serial data output to the digital signal processor
50
CLOK CD
O
Serial data transfer clock signal output to the digital signal processor
51
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder
—
• DVD BOARD IC301 CXP973064-228R (MACHANISH CONTROLLER)
88
HCD-FC7
Pin No.
Pin Name
I/O
Description
53
MUTE DSD
O
Muting on/off control signal output to the DSD decoder “H”: muting on
54
SQCK
O
Subcode Q data reading clock signal output to the digital signal processor
55
VSS
—
Ground terminal (digital system)
56
TRAY IN
I
Disc tray in detection signal input terminal Not used
57
TRAY OUT
I
Disc tray out detection signal input terminal Not used
58
GFS DVD
I
Guard frame sync signal input from the DVD decoder
59
MUTE CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
60
MUTE 2D
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
61
SLED
I
Sled motor servo drive PWM signal input terminal
62
FG
I
Spindle motor control signal input
63
SP ON
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input from the DVD/CD RF amplifier
66
PI
I
Pull in signal input from the DVD/CD RF amplifier
67
FE
I
Focus error signal input from the DVD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
TSD-M
O
Thermal shut down signal output to the motor/coil driver
74
FOK CD
I
Focus OK signal input from the digital signal processor
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output “L”: DVD, “H”: SACD
78
I2C SIO
I/O
Communication data bus with the DVD system processor and system controller
79
IIC-CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the DVD
system processor and system controller
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
SDCLK RF
O
Serial data transfer clock signal output to the DVD/CD RF amplifier
83
SDATA RF
I/O
Two-way data bus with the DVD/CD RF amplifier
84
XWR
O
Write strobe signal output to the DVD decoder
85
XRD
O
Read strobe signal output to the DVD decoder
86
(PWE)
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89 to 96
A0 to A7
O
Address signal output to the DVD decoder
97
A8
O
Motor/coil driver power save control signal output terminal Not used
98
XDRST
O
Reset signal output to the digital signal processor “L”: reset
99
EEP WP
O
Write protect signal output to the EEPROM
100
EEP CLK
O
Clock signal output to the EEPROM
52
SQSO
I
Subcode Q data input from the digital signal processor
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