Sony HCD-FC7 (serv.man2) Service Manual ▷ View online
93
HCD-FC7
Pin No.
Pin Name
I/O
Description
115
SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.6V)
114
SDI3
I
Rear L-ch and R-ch audio serial data input from the digital audio processor
VSS
94
HCD-FC7
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the mechanism controller
3
VSS
—
Ground terminal (digital system)
4
D7
I/O
Two-way data bus with the mechanism controller
5
A0
I
Address signal input from the mechanism controller
6
VDD
—
Power supply terminal (+3.3V) (digital system)
7
A1
I
Address signal input from the mechanism controller
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the mechanism controller
15
VSS
—
Ground terminal (digital system)
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the mechanism controller
18
XWR
I
Write strobe signal input from the mechanism controller
19
XCS
I
Chip select signal input from the mechanism controller
20, 21
XINT0, XINT1
O
Interrupt signal output to the mechanism controller
22
VDD
—
Power supply terminal (+3.3V) (digital system)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DSD decoder and DVD system processor
25
VSS
—
Ground terminal (digital system)
26
HDB8
O
Error flag signal output to the DSD decoder and DVD system processor
27
HDB6
O
Stream data signal output to the DSD decoder and DVD system processor
28
VDDS
—
Power supply terminal (+5V) (digital system)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DSD decoder and DVD system processor
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DSD decoder and DVD system processor
33
VSS
—
Ground terminal (digital system)
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DSD decoder and DVD system processor
36
VDD
—
Power supply terminal (+3.3V) (digital system)
37
HDBC
O
Not used
38
VDDS
—
Power supply terminal (+5V) (digital system)
39
HDB2
O
Stream data signal output to the DSD decoder and DVD system processor
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DSD decoder and DVD system processor
42
VSS
—
Ground terminal (digital system)
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DSD decoder and DVD system processor
45
HDBF
O
Not used
46
XDRQ
O
Serial data effect flag signal output to the DSD decoder and DVD system processor
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XHWR
O
Serial data transfer clock signal output to the DSD decoder and DVD system processor
49
XHRD
O
Header flag signal output to the DSD decoder
50
VDD
—
Power supply terminal (+3.3V) (digital system)
51
REDY
O
Not used
52
VSS
—
Ground terminal (digital system)
• DVD BOARD IC701 TMC57929PGF-RDP (DVD DECODER)
95
HCD-FC7
Pin No.
Pin Name
I/O
Description
53
XHAC
I
DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder
SACD mode: Serial data request signal input from the DSD decoder
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used
66 to 69 MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply terminal (+5V)
73 to 75 MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground terminal (digital system)
91
MA9
O
Address signal output to the D-RAM
92
MNT1
O
EEPROM ready signal output to the mechanism controller
93
MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the mechanism controller
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
96
HCD-FC7
Pin No.
Pin Name
I/O
Description
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
117
RFIN
I
RF signal input from the DVD/CD RF amplifier
118, 119 VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123 GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129 VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134 GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor control signal output
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V) (digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DFCT
I
Defect signal input terminal Not used
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
147
EXCK
O
Subcode serial data reading clock signal output to the digital signal processor
148
SBIN
I
Subcode serial data input from the digital signal processor
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
151
WFCK
I
Write frame clock signal input from the digital signal processor
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used
154
VDDS
—
Power supply terminal (+5V) (digital system)
155
C2PO
I
C2 pointer signal input from the digital signal processor
156
VDD
—
Power supply terminal (+3.3V) (digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
159
DDAT
O
PCM data output terminal Not used
160
MDAT
I
Serial data input from the digital signal processor
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal Not used
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
164
XRST
I
Reset signal input from the mechanism controller “L”: reset
165
IFS0
I
Interface selection signal input terminal Fixed at “L” in this set
166
IFS1
I
Interface selection signal input terminal Fixed at “H” in this set
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