Sony HCD-CZ1 / NAS-CZ1 Service Manual ▷ View online
25
HCD-CZ1/NAS-CZ1
3. bdt RAM WRITE mode
Not used in servicing
4. bdt COMOUT mode
Not used in servicing
5. bdt ERR RATE mode
In bdt ERR RATE mode, N , . and > keys on the main
unit don't work as its normally key function.
unit don't work as its normally key function.
1. Press the
I/
1
button to turn the power on.
2. Insert a CD disc and press the [FUNCTION] button to select
“CD”.
3. Press the N key and select any track with the . / >
keys to play a sample track.
Press the [REPEAT] key on remote commander to set REPEAT
1 mode if you need.
Press the [REPEAT] key on remote commander to set REPEAT
1 mode if you need.
4. Press three buttons of N , [VOL+] and [2] simultaneously.
5. Change the display by pressing the . / > keys to show
5. Change the display by pressing the . / > keys to show
“bdt ERR RATE”.
6. Press the [ENTER] key on remote commander (RM-ANP002).
7. It displays the error rate as follows.
7. It displays the error rate as follows.
Error rate display:
****####$$&&%%
**** : C1 error rate
#### : C2 error rate
$$
#### : C2 error rate
$$
: Track number
&&
: Minutes
%%
: Seconds
Note:
If “C2” value is not “0000” while playing a track, there is
a possibility that sound skipping happens. By comparing
the playability of a track, you can check the disc condition.
a possibility that sound skipping happens. By comparing
the playability of a track, you can check the disc condition.
To back to the servo test menu mode, press the x key on remote
commander.
To release the servo test mode, press the
commander.
To release the servo test mode, press the
I/
1
button to turn the
power off.
Ver. 1.1
26
HCD-CZ1/NAS-CZ1
Note:
1.
CD Block is basically constructed to operate without adjustment.
2.
Use YEDS-18 disc (3-702-101-01) unless otherwise indicated.
3.
Use an oscilloscope with more than 10 M
Ω
impedance.
4.
Clean the object lens by an applicator with neutral detergent when the
signal level is low than specified value with the following checks.
5.
Check the focus bias check when optical block is replaced.
FOCUS BIAS CHECK
Procedure :
1. Connect the oscilloscope to TP (RFACO) and TP (VC) on the
CD board.
2. Insert the disc (YEDS-18). (Part No. : 3-702-101-01)
3. Press the
3. Press the
CD u
button.
4. Confirm that the oscilloscope waveform is as shown in the
figure below. (eye pattern)
A good eye pattern means that the diamond shape (
A good eye pattern means that the diamond shape (
◊
) in the
center of the waveform can be clearly distinguished.
•
RF signal reference waveform (eye pattern)
CD SECTION
SECTION 5
ELECTRICAL ADJUSTMENTS
+
–
–
CD board
TP (RFACO)
TP (VC)
TP (VC)
oscilloscope
(DC range)
Checking Location:
VOLT/DIV: 0.2 V (with the 10: 1 probe in use.)
TIME/DIV: 500 ns
TIME/DIV: 500 ns
1.1
When observing the eye pattern, set the oscilloscope
for AC range and raise vertical sensitivity.
for AC range and raise vertical sensitivity.
0.2 Vp-p
TP
(RFACO)
TP (VC)
– CD BOARD (Conductor Side) –
HCD-CZ1/NAS-CZ1
27
27
HCD-CZ1/NAS-CZ1
SECTION 6
DIAGRAMS
6-1. BLOCK DIAGRAM – SERVO SECTION –
MIACK
8
PO11/BUCK/AD14
36
MILP
5
RESET
2
MICS
4
MIDIO
6
MICK
7
MP3 DECODER
IC301
A/D
CONVERTER
CH2OUTF
CH2OUTR
23
24
21
4
5
6
7
17
18
16
15
RFACI
ASYO
ASYI
FILTER
FILO
PCO
CLTV
FILI
DIGITAL PLL
ASYMMETRY
CORRECTOR
EFM
DEMODULATOR
CD DSP
IC101 (1/2)
MDP
DIGITAL
CLV
PROCESSOR
32K
RAM
ERROR
CORRECTOR
INTERNAL BUS
SQCK
SQSO
EXCK
AOUT1
C4M
XTSL
XTAO
XTAI
AOUT2
R-CH
D/A
DIGITAL
INTERFACE
D/A
CONVERTER
SELECTOR
CLOCK
GENERATOR
SUBCODE
PROCESSOR
SCOR
WFCK
XUGF
GFS
EMPH
SENS
DATA
CLOCK
XLAT
SBSO
I-SENS
O-DATA
O-XLT
TEI
FEI
FOCUS/
TRACKING/SLED
SERVO DSP
FOCUS/TRACKING/SLED
PWM GENERATOR
SFDR
CH3FIN
CH4IN
CH3RIN
CH3OUTF
CH3OUTR
CH1FIN
CH1RIN
CH2FIN
CH2RIN
20
MUTE
SRDR
TFDR
TRDR
FFDR
FRDR
SSTP
COUT
MIRR,
DFCT, FOK
DETECTOR
SERVO AUTO
SEQUENCER
SERVO
INTERFACE
CPU INTERFACE
SCLK
TO CPU INTERFACE
FOK
MIRR
DFCT
2
OPIN+
CH4OUTF
CH4OUTR
27
OPOUT
M101
(SPINDLE)
MOTOR
DRIVE
MOTOR
DRIVE
COIL
DRIVE
CH1OUTF
CH1OUTR
COIL
DRIVE
M
M
M102
(SLED)
MOTOR/COIL DRIVE
IC251
2-AXIS
DEVICE
(TRACKING)
(FOCUS)
CD DSP
IC101 (2/2)
•
SIGNAL PATH
: CD PLAY
14
13
11
12
I-SCOR
A
(Page 29)
CD-L
13
11
12
9
10
14
119
108
21 23
3
1
2
7
TO SERVO AUTO
SEQUENCER
42
51 53
XPCK
112
50 52
45
46
6
XRST
100
O-XRST
73
96 97
81
78
117
93
77
86
98 99
115
107
102 105 104
110 111 113 68
53
O-CLOCK
54 69
LRCK
BCK
PCMD
LRCKIA
SDI0
63 66 65
16
BCKIA
15
SFSY/LRCKIB
19
SBSY/BCKIB
18
14
LRCKI
BCKI
PCMDI
SDO0
62 60 61
11
52 58
26
27
28
29
24
22
20
19
37
36
E
B
A
D +3.3V
F
DETECTOR
A
B
C
D
RF
SUMMING
AMP
FOCUS
ERROR
AMP
TRACKING
ERROR AMP
RFACO
FEO
TEO
E
F
AUTOMATIC
POWER
CONTROL
Q10
APC LD
AMP
LD
LD
PD
LASER DIODE
OPTICAL PICK-UP
BLOCK
(KSM-213EDP)
PD
I-V AMP
D
C
EQ_
IN
41
35
34
EQ
AC_
SUM
RFAC
VCA
X171
16.9344MHz
SYSTEM CONTROLLER
IC601 (1/3)
S101
(LIMIT)
I-MP3DATA 55
O-MP3DATA 56
O-MP3CLK 57
O-MICS 85
I-MP3_ACK 83
I-MP3_REQ 82
O-MILP 84
O-MP3RST 86
O-XTCN 70
CD_OPEN_CLOSE 75
STANDBY
3
I-MP3_STBY 81
• R-ch is omitted due to same as L-ch.
XTACN
95
DISC LID
OPEN DETECT
S601
HCD-CZ1/NAS-CZ1
28
28
HCD-CZ1/NAS-CZ1
6-2. BLOCK DIAGRAM – ETHERNET SECTION –
79
78
77
76
17
18
TXD0
DOUT
VOUTL
E-LOUT
R-CH
PDOWN
NRESET
IICDATA
IICCLK
VOUTR
DIN
BCKIN
BCKIN
MCLK
LRCK
LRCK
MUTEB
SDIDEM
SDIDEM
TXD1
TXD2
TXD3
TXD3
80 TXEN_N
82 TXCLK_N
83 TXER_N
75 COL_N
74 CRS_N
82 TXCLK_N
83 TXER_N
75 COL_N
74 CRS_N
89 RXD0
91 RXD1
92 RXD2
93 RXD3
91 RXD1
92 RXD2
93 RXD3
87
68
RXDV_N
86 RXCLK_N
84 RXER_N
94 MDC
95 MDIO
84 RXER_N
94 MDC
95 MDIO
2 PIOC1
RAS
MD0-15
MD0-15
MA1-19
MA1-19
MA1-12
CAS
LDQM
LDQM
UDQM
CLK
CKE
CKE
WE
CS
CS
RAS
CAS
LDQM
UDQM
CLK
CKE
CKE
WE
CS
OE
3 PIOC2
17
18
19
20
TXD0
TXD1
TXD2
TXD3
TXD3
16
TXEN
15
TXC/REF_CLK
14
TXER
21
COL/RMII
22
CRS/RMII_LPBK
NC
RXD–
RXD+
TXD–
TXD+
NC
6
RXD0/PHYAD4
5
RXD1/PHYAD3
4
RXD2/PHYAD2
3
RXD3/PHYAD1
9
RXDV/PCS_LPBK
10
RXC
11
46
45
RXER/ISO
2
MDC
1
MDIO
30
PD#
48
RST#
108
BCLK 109
MCLK 110
LRCK 107
PIOC7 127
PIOC0 1
2
3
4
11
8
1
PIOC8
XRASN
XA1-19
XD0-15
67
XCASN
73
XDQM0
72
XDQM1
69
XSDCLK
71
XSDCKE
58
XWEN
70
XSDCSN
57
XOEN
17 RAS
A0-11
A0-15
DQ0-15
DQ0-15
16 CAS
14 LDQM
77 ETHER-PDOWN
37 I2C_DATA
38 I2C_CLK
76 ETHER-NRESET
36 UDQM
35 CLK
34 CKE
15 WE
18 CS
FLASH MEMORY
IC504
SD-RAM
IC503
SYSTEM CONTROLLER
IC601(2/3)
ETHERNET CONTROLLER
IC502
D/A CONVERTER
IC505
ETHERNET INTERFACE
IC501
+2.5V REGULATOR
IC506
PULSE
TRANSFORMER
T501
11 WE
28 OE
12 RST
RESETN
128
114
115
124
125
PIOC4/SDA/SDI1 102
PIOC5/SCL/SCLK1 101
122
8-14,16,26,
25,23-20,
18,17
53-56,42-37,
50,48,47,45,
44,27,29,30,35
2,3,5,6,8,9,
11,12,39,40,42,
43,45,46,48,49
21-24,
27-32,
27-32,
20,19
29-36,
38-45
24-16,
8-1
X502
24.576MHz
OSC1N
OSC1
X501
25MHz
XI
XO
41 TX+
38
VDDRCV
(2.5V SUPPLY)
(2.5V SUPPLY)
40 TX–
X503
11.2896MHz
OSC0N
+2.5V
EVER+3.3V
OSC0
33 RX+
32 RX–
1
2
6
3
4, 5
7, 8
1
16
J501
(ETHERNET)
14
15
11
9
10
2
3
3
6
7
7
8
•
SIGNAL PATH
: ETHERNET
B
(Page 29)
•
R-ch is omitted due to same as L-ch.
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