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— 41 —
5-5. Clock System
Mode
Analog recording/playback
Digital recording
Fs (Hz)
48 k
44.1 k
32 k
48 k/44.1 k/32 k
Fig. 5-8. Clock System Diagram
Fig. 5-8.
shows the clock system diagram and
Fig. 5-9.
shows the block diagram of the Fs system clock used for the
signal circuit of this unit. The system (master) clock is supplied to the main microprocessor (IC501), mechanism
microprocessor (IC502), and slave DAT DSP (IC803, PCM-2800 only) from the DAT DSP (IC503) as shown in the
figure. The main microprocessor and mechanism microprocessor are supplied with 9.4 MHz which is obtained by
frequency dividing the 18.8 MHz of X502 connected to Pins !£ and !¢ by 1/2 divider (IC519).
The DAT DSP (IC503) is equipped with such functions as recording/playback digital signal processing, RAM control,
digital I/O signal processing, and functions to generate the Fs system clock such as BCK (bit clock) and LRCK (L/R
clock) to be supplied to the digital signal circuit. In the operation mode of each clock serving as the reference, the X501,
X301, and X302 reference oscillations are switched according to the sampling frequency during analog recording and
playback. During digital recording, the 512 fs obtained by RX PLL is used as the reference frequency as shown in
microprocessor (IC502), and slave DAT DSP (IC803, PCM-2800 only) from the DAT DSP (IC503) as shown in the
figure. The main microprocessor and mechanism microprocessor are supplied with 9.4 MHz which is obtained by
frequency dividing the 18.8 MHz of X502 connected to Pins !£ and !¢ by 1/2 divider (IC519).
The DAT DSP (IC503) is equipped with such functions as recording/playback digital signal processing, RAM control,
digital I/O signal processing, and functions to generate the Fs system clock such as BCK (bit clock) and LRCK (L/R
clock) to be supplied to the digital signal circuit. In the operation mode of each clock serving as the reference, the X501,
X301, and X302 reference oscillations are switched according to the sampling frequency during analog recording and
playback. During digital recording, the 512 fs obtained by RX PLL is used as the reference frequency as shown in
Table
5-3.
X501 (24.5 MHz) functions as the reference oscillation during analog recording and playback based on a sampling
frequency of 32 kHz. It is also used as a DAT DSP system clock, and is generated in all modes.
frequency of 32 kHz. It is also used as a DAT DSP system clock, and is generated in all modes.
Table 5-3. Fs System Reference Clock Operation Mode
4
RX VCO
(512 Fs)
G
G
G
G
G
2
X301
(24.5 MHz)
G
G
G
G
G
1
X501
(24.5 MHz)
®
®
®
®
(
®:Oscillation G:Oscillation stopped: :fs reference oscillation)
SLAVE
DAT DSP
IC803
67
66
14
13
24M
XT1I
XT1O
18M
67
66
14
13
XT1I
XT1O
DAT DSP
IC503
X501
24.576MHz
XT3I
XT3O
X502
18.816MHz
11
Q
9
Q
12
8
D
1/2 DIVIDER
IC519
MECHA MICON
(SERVO PROCESS)
IC502
MAIN MICON
IC501
43
77
EXTAL
MST-CLK
43
EXTAL
9.4M
PCM-2800
XT3I
XT3O
3
X302
(22.5 MHz)
G
G
G
G
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Table 5-4. Relation between Sampling Frequency and FSEN
Digital recording
Analog recording
playback
FSEN
L
H
H
Fs (Hz)
48 k/44.1 k
32 k
48 k/44.1 k/32 k
XFSEN
H
L
L
For the reference oscillation during analog recording, the X501 (24.5 MHz) connected to Pins ^§ and ^¶ of the DAT
DSP is switched and used during a sampling frequency of 32 kHz (LP mode). For sampling frequencies 48 kHz and 44.1
kHz, X301 (24.5 MHz) and X302 (22.5 MHz) are switched and used. This switching is performed by the Fs switching
signal output from Pins @ • to # º (FS48 to FS32) of the main microprocessor. The flow of the Fs clock signals is
controlled by the FSEN and XFSEN signals shown in
DSP is switched and used during a sampling frequency of 32 kHz (LP mode). For sampling frequencies 48 kHz and 44.1
kHz, X301 (24.5 MHz) and X302 (22.5 MHz) are switched and used. This switching is performed by the Fs switching
signal output from Pins @ • to # º (FS48 to FS32) of the main microprocessor. The flow of the Fs clock signals is
controlled by the FSEN and XFSEN signals shown in
Table 5-4
.
The FSEN signal inputs to the gate circuit (IC514, IC515) outputs from the Pin #º of the main microprocessor (FS32,
“H” when Fs is 32 kHz), Pin 9 (VCOEN, “H” during digital IN recording), Pin #¡ of DAT DSP (UNLK, “L” when RX
PLL is in the locked state), and outputs them from Pin 8 of IC515 to the 1/2 divider (IC309) and DAT DSP, etc. The
XFSEN signal on the other hand is the reversed signal of FSEN inside the D/A converter (IC314), and is output from Pin
$ª of the D/A converter to the 1/2 divider (IC309) SBM digital filter (IC308). These two signals switch the inputs and
output of the Fs clocks (BCK, LRCK, etc.) of the DAT DSP and SBM digital filters and switch the transmission
direction of the clock buffer (IC313). The 1024 fs with high purity (little jitter components) obtained using the VCO
(Q307, 308) with LRCK as the reference frequency is used as the master clock of the D/A converter (IC314) to improve
the S/N ratio and sound quality.
The following shows the flow of the Fs clock signals during the respective modes.
“H” when Fs is 32 kHz), Pin 9 (VCOEN, “H” during digital IN recording), Pin #¡ of DAT DSP (UNLK, “L” when RX
PLL is in the locked state), and outputs them from Pin 8 of IC515 to the 1/2 divider (IC309) and DAT DSP, etc. The
XFSEN signal on the other hand is the reversed signal of FSEN inside the D/A converter (IC314), and is output from Pin
$ª of the D/A converter to the 1/2 divider (IC309) SBM digital filter (IC308). These two signals switch the inputs and
output of the Fs clocks (BCK, LRCK, etc.) of the DAT DSP and SBM digital filters and switch the transmission
direction of the clock buffer (IC313). The 1024 fs with high purity (little jitter components) obtained using the VCO
(Q307, 308) with LRCK as the reference frequency is used as the master clock of the D/A converter (IC314) to improve
the S/N ratio and sound quality.
The following shows the flow of the Fs clock signals during the respective modes.
(1) During analog recording/playback when Fs is 44.1/48 kHz (See Fig. 5-10.)
When the sampling frequency is 48 kHz, Pin @• of the main microprocessor becomes “H”, X301 operates and is used as
the reference oscillation. When the sampling frequency is 44.1 kHz, X302 serves as the reference oscillation in the same
way.
During this time, Pins 9 and #º of the main microprocessor are both “L”. Therefore FSEN becomes “L” and XFSEN
becomes ‘’H”, and the SBM digital filter (IC308) outputs the Fs clock.
the reference oscillation. When the sampling frequency is 44.1 kHz, X302 serves as the reference oscillation in the same
way.
During this time, Pins 9 and #º of the main microprocessor are both “L”. Therefore FSEN becomes “L” and XFSEN
becomes ‘’H”, and the SBM digital filter (IC308) outputs the Fs clock.
(2) During analog recording/playback when Fs is 32 kHz (See Fig. 5-11.)
In this mode, X501 serves as the reference oscillation of the Fs clock. Because Pin #º of the main microprocessor (FS32)
is “H”, FSEN becomes “H” and DAT DSP outputs the Fs clock. During this time, the system clock to the A/D converter
(IC307) is 128 fs obtained by frequency dividing 1024 fs (VCO Q307, 308) created in the PLL circuit based on the
LRCK in the D/A converter, 1/2 divider (IC309), and SBM digital filter. This system clock is supplied from Pin @§
(FCLK) of the SBM digital filter.
is “H”, FSEN becomes “H” and DAT DSP outputs the Fs clock. During this time, the system clock to the A/D converter
(IC307) is 128 fs obtained by frequency dividing 1024 fs (VCO Q307, 308) created in the PLL circuit based on the
LRCK in the D/A converter, 1/2 divider (IC309), and SBM digital filter. This system clock is supplied from Pin @§
(FCLK) of the SBM digital filter.
(3) During digital recording (See Fig. 5-12.)
In this mode, the 512 fs input to Pin $• (PLCO) of the DAT DSP from RX VCO is used as the reference oscillation.
Because “H” is output from Pin 9 of the main microprocessor and “L” is output from Pin #¡ of DAT DSP when the RX
PLL locks, FSEN becomes “H” and DAT DSP outputs the Fs clock. When the RX PLL lock is released, Pin #¡ of DAT
DSP becomes “H”. When the sampling frequency of the digital input signal is 44.1 kHz or 48 kHz, the same operations
as (1) above are performed. When 32 kHz, the same operations as (2) are performed.
Because “H” is output from Pin 9 of the main microprocessor and “L” is output from Pin #¡ of DAT DSP when the RX
PLL locks, FSEN becomes “H” and DAT DSP outputs the Fs clock. When the RX PLL lock is released, Pin #¡ of DAT
DSP becomes “H”. When the sampling frequency of the digital input signal is 44.1 kHz or 48 kHz, the same operations
as (1) above are performed. When 32 kHz, the same operations as (2) are performed.
Mode
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