Sony DTC-A8 / PCM-2600 / PCM-2800 Service Manual ▷ View online
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5-6. Operations During Recording
The Lch and Rch analog signals input to Pins @∞ and @§ and Pins 3 and 4 of the A/D converter (IC307) are each
converted to 24-bit quantize digital data by
converted to 24-bit quantize digital data by
G64 oversampling , and output to the SBM digital filter (IC308) as PDM
(pulse density modulation) 1 bit data from Pins @¡ and 8. In the SBM digital filter, SBM signal processing is performed
on 24 bit digital data, and after conversion to 16-bit, the signals synchronized with the bit clock (BCK) and L/R clock
(LRCK) and are output from Pin %º (DLO) according to the timing shown in
on 24 bit digital data, and after conversion to 16-bit, the signals synchronized with the bit clock (BCK) and L/R clock
(LRCK) and are output from Pin %º (DLO) according to the timing shown in
Fig. 5-13
.
In the case of digital input, the digital signal input to Pin %™ (RX) of DAT DSP (IC503) is transmitted to the RX PLL
and digital IN demodulation circuit to extract only the audio signals. It is then output from Pin &ª (ADDI).
The switching of the analog and digital signals is performed by the switching signal (L : analog, H : digital) output from
Pin !∞ (XANA/DIG) of the main microprocessor (IC501) in the selector (IC511) via D-FF (IC512), and is output to Pins
&§ and *º of the DAT DSP. When this switching is performed according to the timing of LR01 (15BCK delay signal of
LRCK) based on the switching signal from the main microprocessor, noises are eliminated. (For details of the operations
of the selector (IC511), see
and digital IN demodulation circuit to extract only the audio signals. It is then output from Pin &ª (ADDI).
The switching of the analog and digital signals is performed by the switching signal (L : analog, H : digital) output from
Pin !∞ (XANA/DIG) of the main microprocessor (IC501) in the selector (IC511) via D-FF (IC512), and is output to Pins
&§ and *º of the DAT DSP. When this switching is performed according to the timing of LR01 (15BCK delay signal of
LRCK) based on the switching signal from the main microprocessor, noises are eliminated. (For details of the operations
of the selector (IC511), see
Table 5-5.
Table of Truth Values.)
As for DAT DSP, MAIN-ID, SUB-ID, sub data (PACK data), etc. is input to Pin @¢ as a serial data (SDSI) synchronized
with the clock (EXCK) from the main microprocessor. The signals are interleaved by the DAT DSP and SRAM (IC504),
added with C1 parity, C2 parity, 8-10 modulated, added with the ATF signal, and output from Pin $£.
Inside the RF amplifier (IC1), the recorded data (REDT) is amplified. After this, the recording signals are transmitted
alternately to heads A and B according to the timing of the switching pulse (SWP) and recording/playback discrimination
signal (REPB) as shown in
with the clock (EXCK) from the main microprocessor. The signals are interleaved by the DAT DSP and SRAM (IC504),
added with C1 parity, C2 parity, 8-10 modulated, added with the ATF signal, and output from Pin $£.
Inside the RF amplifier (IC1), the recorded data (REDT) is amplified. After this, the recording signals are transmitted
alternately to heads A and B according to the timing of the switching pulse (SWP) and recording/playback discrimination
signal (REPB) as shown in
Fig. 5-14.
and recorded in tape.
The PIPC signal output from the RF amplifier from Pin $¡ of DAT DSP indicates the recording range of the ATF pilot
signal. Based on this signal, the RF amplifier recording current is set.
signal. Based on this signal, the RF amplifier recording current is set.
Fig. 5-13. Audio Signal Timing
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Fig. 5-14. Waveform Timing (SP Mode) During Recording
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