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— 37 —

• PB AMP

The PB AMP is low noise amplifier with 40 dB (43 dB in half speed mode) in the normal mode.

• SWITCH AMP

Switches the output from the 2ch PB AMP according to logic and outputs to Pin @¡ (SWA OUT).

• PILOT FILTER

Filter for extracting the ATF pilot signal from the playback RF signal. The input pin (@º EQ IN) is shared with the
PCM equalizer. Signals are output from Pin !£ (FLT OUT).

• PILOT GCA

Adjusts the gain according to the control voltage to Pin !¢ (GCA CTL).

• PILOT ENVELOPE DET

Inputs signals from the pilot GCA and detects and output envelopes according to the two-wave rectification.

• PB LIMIT

Inputs the EQ output to Pin 9 (LIM IN), changes it to rectangular wave with about 870 mVp-p amplitude, and output
it.

• RF ENVELOPE DET

Inputs the EQ output to Pin 9 (LIM IN), performs envelope detection, and outputs “L” for envelopes below 1/2 of
the envelope peak level and “H” above 1/2 in the comparator.

The operation mode of the recording/playback amplifier CXA1364R is switched as shown in 

 by REPB (REC/

PB selection signal, set to recording at “H”) from the DAT DSP CXD2605Q (IC503). The SWP (switching pulse) from
the mechanism microprocessor (servo process, IC502) is used by the SWITCH AMP which switches the outputs from the
A/B PB AMP during playback according to the SWP timing.

Recording

Playback

$∞

$¶

L

H

L : Head A is in recording mode
H : Head B is in recording mode

L : Head A is in playback mode
H : Head B is in playback mode

— 38 —

LIM OUT

LIM GND

MODE1 IN

MODE2 IN

LIM VCC

ENV OUT

ENV COMP

ENV PEAK

LIM IN

EQ OUT

P EV OUT

P EV IN

FLT OUT

GCA CTL

EQ PHASE

EQ Q

EQ HIGH

EQ LOW

PB GND

EQ IN

SWA OUT

V REG

B HA OUT

B LPC

B PC

B HA IN

B RA OUT

HA GND

REC GND

REC BIAS

HA VCC

REC VCC

A RA OUT

A HA IN

A PC

ALPC

A HA OUT

SAG TC

A R PCM

B R PCM

A R PLT

B R PLT

PB VCC

REDT IN

REC/PB IN

PIPC IN

SWP IN

NRR HLF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

O

–

I

I

–

O

I

O

O

I

O

I

–

I

O

O

I

O

–

–

I

–

–

O

I

O

–

I

I

I

I

I

PB Limiter output pin

PB Limiter and RF Envelope Detector GND pin

Operation mode selection logic input pin

Operation mode selection logic input pin

PB limiter and RF envelope detection Vcc pin

RF envelope detection output pin

Pin for adjusting RF envelope threshold voltage

Pin connected to capacitor for holding RF peak

PB limiter and RF envelope detection input pin

PCM equalizer output pin

Pilot envelope output pin as well as pin connected to capacitor for peak holding

Pilot GCA input pin

Pilot filter output pin

Pilot GCA gain control voltage input pin

With resistor or current source for determining PCM EQ phase characteristics.

With resistor and current source for determining PCM EQ high range peak amount.

With resistor and current source for determining PCM EQ high range peak frequency and Pilot Filter cutoff frequency.

With resistor and current source for determining PCM EQ low range characteristics.

Head amplifier and limiter, and PB circuit other than RF envelope detection circuit, logic, and regulator GND pin

PCM EQ input pin

Switch amplifier output pin

Regulator output pin with smoothing capacitor

Bch head amplifier output pin

Bch head amplifier DC servo DC smoothing capacitor connection pin

Bch head amplifier pass control connection pin

Bch head amplifier input pin

Bch REC amplifier output pin

Head amplifier GND pin

REC amplifier GND pin

REC final stage amplifier input pin connected with resistor supplying bias and feedback resistor from output.

Head amplifier Vcc pin

REC amplifier Vcc pin

Ach REC amplifier output pin

Ach head amplifier input pin

Ach head amplifier pass control connection pin

Ach head amplifier DC servo DC smoothing capacitor connection pin

Ach head amplifier output pin

Pin for connecting capacitor for correcting recording waveform sag

Connection pin of the resistor for determining Ach recording current.

Connection pin of the resistor for determining Bch recording current.

Connection pin of the resistor for determining Ach pilot signal recording current together with Pin 39 resistor.

Connection pin of the resistor for determining Bch pilot signal recording current together with Pin 40 resistor.

Head amplifier and limiter, and PB circuit other than RF envelope detection circuit, logic, and regulator Vcc pin

Recording signal input pin

Recording/playback switching signal input pin

PCM pilot recording area selection signal input pin

A/Bch selection switching signal input pin

Normal speed/half speed selection signal input pin

— 39 —

During digital recording, the digital audio interface format signal transmitted from the transmission side device is input
from the AES/EBU (J801) or COAXIAL (J501), the input is switched by S501 connected to the DIGITAL IN
SELECTOR (IC508), and the signal is input to Pin %™ (RX) of the DAT DSP CXD2605Q. The feedback circuit (IC509)
connected between Pins 5 and 6 of IC508 is called the normalizer. To maintain the duty ratio of the digital input signal
to Pin %™ (RX) at 50% constantly, it converts the digital input signal to a direct current using the resistor and capacitor
connected to Pin 3, and imposes the DC servo so that the threshold potential (V

DD

) is maintained at 1/2 V

DD

.

In addition, the DAT DSP, external RX VCO (IC513), and RX PLL circuit carry out phase comparison with the 2 fs
obtained by frequency dividing the SYNC extracted from the digital input signal (preamble) and RX VCO, generate 512
fs synchronized with the SYNC of the digital input signal, and use it for data demodulation and Fs system clock.

RX

VCO

1/256

48

PLCO

49

PLVR

45

PDO

PC

2fs

SYNC

DET

2fs

NAND GATE
IC514

31

UNLK

1 12 13

(L:LOCK)

DATA

DEMODULATION

79

ADDI

SIGNAL SELECT

IC511   11

52

RX

DAT DSP

CXD2605Q

IC503

2

LPF

1

IC513

512fs

512fs

50

PLRF

V

1/2

3

2

4

5

6

IC508

NORMALIZER

IC509

12

11

AES/EBU

J801

VDD

S501

COAXIAL

AES/EBU

D508

D509

BUFFER

IC510

2

3

IC801

MAIN MICON

IC501       VCOEN

9

(H:DIGITAL IN REC)

1

2

3

DIGITAL IN SELECTOR

IC508

8

9

10

11

12

13

COAXIAL

J501

DIGITAL

IN

11

12

13

MAIN MICON

IC501       XAES/COA

71

(L:AES/EBU)

1

1

2

3

4

DD

V

DD

+

–

— 40 —

When the RX PLL is in the locked state, the PLL reference (%º PLRF) of the 2 fs obtained from the SYNC of the digital
signal and PLL variable ($ª PLVR) of the 2 fs obtained by frequency dividing RX VCO as shown by the waveform
timing in 

 have the phase relation shown in the same diagram, and Pin #¡ (UNLK) which indicates the lock state

of RX PLL becomes “L”.
The AES/EBU side of the input selection switch (S501) is connected to Pin &¡ (XAES/COA) of the main microprocessor
(IC501). It is used for switching the audio interface format (AES/EBU or consumer use) of the digital IN/OUT signal
and for switching the display of the FL display tube.
When performing digital recording by selecting COAXIAL or OPTICAL using DTC-A8, “recording of digital signals
directly” will conform to the standards of SCMS (serial copy management system) which sets the restriction (to 1st
generation).