Sony DHC-FLX5D / DHC-FLX7D / HCD-FLX5D / HCD-FLX7D Service Manual ▷ View online
109
HCD-FLX5D/FLX7D
DSP BOARD IC601 CXD9720Q (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the digital audio interface receiver “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
5
VDDI
—
Power supply terminal (+3.3V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13 MHz)
10
VDDI
—
Power supply terminal (+3.3V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13 MHz)
13
MS
I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
18
SDI1
I
Audio serial data input from the digital audio interface receiver or digital audio processor
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
GP12
O
Clock signal output terminal Not used
38
GP13
O
Clock enable signal output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+3.3V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
110
HCD-FLX5D/FLX7D
Pin No.
Pin Name
I/O
Description
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot trap signal input from the digital audio interface receiver
57
MOD1
I
PLL input frequency select terminal “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+3.3V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
Not used
Not used
68
DECODE
O
Decode signal output to the system controller
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+3.3V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used
88
XTRST
I
Simple emulation asychronous break input terminal Not used
89
TCK
I
Simple emulation clock signal input terminal Not used
90
TDI
I
Simple emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+3.3V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
111
HCD-FLX5D/FLX7D
Pin No.
Pin Name
I/O
Description
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL reset signal input from the digital audio interface receiver
114
SDI3
I
Audio serial data input from the digital audio processor (FLX7D only)
115
SDI4
I
Audio serial data input from the digital audio processor (FLX7D only)
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117
TST2
—
Ground terminal
118
GP11
—
Not used
119
TST3
—
Ground terminal
120
VDDI
—
Power supply terminal (+3.3V)
112
HCD-FLX5D/FLX7D
MC BOARD IC101 M3062CMEN-A05FPU0 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61520FP
2
AMP-CLK
O
Serial data transfer clock signal output to the M61520FP
3
AMP-LAT
O
Serial data latch pulse signal output to the M61520FP
4
SIRCS
I
Remote control signal input from the remote control receiver
5
DIG-TX
O
Serial data output to the audio digital signal processor and digital audio interface receiver
6
DSP-RX
I
Serial data input from the digital audio interface receiver
7
DIG-CLK
O
Serial data transfer clock signal output to the audio digital signal processor and
digital audio interface receiver
digital audio interface receiver
8
GND
—
Ground terminal
9
GND
—
Not used
10
XC-IN
I
Sub system clock input terminal (32.768 kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal input terminal Not used
19
SCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used
20
DIR-INT
O
Interrupt request signal output to the digital audio interface receiver
21
CAPM-H/L
O
High/normal speed selection signal output of the capstan motor
“L”: high speed, “H”: normal speed
“L”: high speed, “H”: normal speed
22
CAPM-CNT1
O
Capstan motor drive signal output
23
A TRG
O
Deck-A side trigger plunger drive signal output “H”: plunger on
24
BU-PWM3
O
RFDC PWM signal output terminal Not used
25
B TRG
O
Deck-B side trigger plunger drive signal output “H”: plunger on
26
BU-PWM2
O
PWM signal output terminal Not used
27
A-HALF
I
Deck-A cassette detection signal input terminal “L”: no cassette, “H”: cassette in
28
BU-PWM1
O
Focus servo drive PWM signal output terminal Not used
29
IIC-CLK
I/O
IIC data reading clock signal input or transfer clock signal output with the fuluorescent indicator
driver and DVD system processor
driver and DVD system processor
30
IIC-DATA
I/O
IIC two-way data bus with the fuluorescent indicator driver
31
CAN'T USE
I
Not used
32
SQ-DATA-IN
I
Subcode Q data input terminal Not used
33
SQ-CLK
O
Subcode Q data reading clock signal output terminal Not used
34
SENS
I
Internal status detection monitor input terminal Not used
35
CD-DATA
O
Serial data output terminal Not used
36
CAN'T USE
I
Not used
37
CD-CLK
O
Serial data transfer clock signal output terminal Not used
38
POWER LED
O
LED drive signal output terminal
39
CLOCK-OUT
O
Clock (32.768 kHz) signal output terminal (for test mode) Not used
40
LDON(3STATE)
O
Laser diode on/off control signal output terminal Not used
41
M-RESET
I
Reset signal output to the fluorescent indicator tube driver and front panel controller
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