Sony DHC-FLX5D / DHC-FLX7D / HCD-FLX5D / HCD-FLX7D Service Manual ▷ View online
105
HCD-FLX5D/FLX7D
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used
61
PHREFI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
62
PHREFO
O
Bit clock signal (2.8224 MHz) output to the digital audio processor
63
ZDFL
O
Front L-ch Zero data flag detection signal output terminal Not used
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output terminal Not used
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
67
VDDSD0
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal Not used
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output terminal Not used
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output terminal Not used
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output terminal Not used
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface Not used
80
VSCB0
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface Not used
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface Not used
86
VSIOB0
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface Not used
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip interface Not used
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip interface
Not used
Not used
90
VDIOB0
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface Not used
93
IBCK
O
Data transmission clock signal output terminal for IEEE 1394 link chip interface Not used
94
VSCB1
—
Ground terminal (for core)
95
IERR
I
Not used
96
IANCI
I
Not used
97
IPLAN
I
Not used
98
IHOLD
O
Not used
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105 IDIN0 to IDIN4
I
Not used
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109 IDIN5 to IDIN7
I
Not used
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection Not used
115
TESTI
I
Input terminal for the test (normally: fixed at “L”)
116
VSCB2
—
Ground terminal (for core)
106
HCD-FLX5D/FLX7D
Pin No.
Pin Name
I/O
Description
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection Not used
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
122
WRFD
I
Not used
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the DVD decoder
124, 125
WAVDD0,
WAVDD1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the DVD/CD RF amplifier
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS0, WAVSS1
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIOA2
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the SD-RAM
135
VDIOA2
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
DQ3 to DQ0
I/O
Two-way data bus with the SD-RAM
140
VSIOA3
—
Ground terminal (for I/O)
141
DCLK
O
Clock signal output to the SD-RAM
142
DCKE
O
Clock enable signal output to the SD-RAM
143
XWE
O
Write enable signal output to the SD-RAM
144
XCAS
O
Column address strobe signal output to the SD-RAM
145
XRAS
O
Row address strobe signal output to the SD-RAM
146
VDIOA3
—
Power supply terminal (+3.3V) (for I/O)
147
NC
O
Not used
148, 149
A11, A10
O
Address signal output to the SD-RAM
150
VSCA3
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the SD-RAM
153
VDCA3
—
Power supply terminal (+2.5V) (for core)
154 to 157
A7 to A4
O
Address signal output to the SD-RAM
158
VSIOA4
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the SD-RAM
163
VDIOA4
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the DVD decoder
165
XSHD
I
Header flag signal input from the DVD decoder
166
SDCK
I
Serial data transfer clock signal input from the DVD decoder
167
XSAK
I
Serial data effect flag signal input from the DVD decoder
168
SDEF
I
Error flag signal input from the DVD decoder
169 to 176
SD0 to SD7
I
Stream data signal input from the DVD decoder
107
HCD-FLX5D/FLX7D
MB BOARD IC901 CXP973064-236R (MACHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
EEP SO
O
Not used
2
SDEN
O
Serial data enable signal output to DVD/CD RF amplifier
3
DOCTRL/
ISBTEST
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
EEP WC
O
Not used
5
EEP SI
I/O
Two-way data bus with the EEPROM
6
EEP RDY
I
EEPROM ready signal input from the DVD decoder
7
FCS JMP 1
O
Focus jump 1 signal output to the motor/coil driver
8
FCS JMP 2
O
Focus jump 2 signal output to the motor/coil driver
9
SENS CD
I
Internal status (SENSE) signal input from the digital signal processor
10
LOAD +
O
Loading motor drive signal (loading in direction) output terminal Not used
11
LOAD –
O
Loading motor drive signal (loading out direction) output terminal Not used
12
XCS DVD
O
Chip select signal output to the DVD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the DVD decoder
22
INIT0 DVD
I
Interrupt signal input from the DVD decoder
23
INIT1 DVD
I
Interrupt signal input from the DVD decoder
24
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder
25
XRST DVD
O
Reset signal output to the DVD decoder “L”: reset
26
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor (FLX7D only)
27
LAT CD
O
Serial data latch pulse signal output to the digital signal processor
28
LD ON
O
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
29
MIRR
I
Mirror signal input from the digital signal processor
30
COUT CD
I
Numbers of track counted signal input from the digital signal processor
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS ZIVA
O
Chip select signal output to the DVD system processor
33
SI ZIVA
I
Serial data input from the DVD system processor
34
SO ZIVA
O
Serial data output to the DVD system processor
35
SCK ZIVA
O
Serial data transfer clock signal output to the DVD system processor
36
DRVIRQ
O
Interrupt request signal output to the DVD system processor
37
DRVRDY
O
Ready signal output to the DVD system processor
38
RST
I
System reset signal input from the DVD system processor “L”: reset
39
VSS
—
Ground terminal (digital system)
40
XTAL O
System clock output terminal (20 MHz)
41
EXTAL I
System clock input terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43, 44
SLED A, SLED B
O
Sled motor drive signal output
45
JIT OFFSET
O
Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
46
SDOUT DSD
O
Serial data output to the DSD decoder (FLX7D only)
47
SDIN DSD
I
Serial data input from the DSD decoder (FLX7D only)
48
READY DSD
I
Ready signal input from the DSD decoder “L”: ready (FLX7D only)
49
DATA CD
O
Serial data output to the digital signal processor
50
CLOK CD
O
Serial data transfer clock signal output to the digital signal processor
51
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder (FLX7D only)
108
HCD-FLX5D/FLX7D
Pin No.
Pin Name
I/O
Description
52
SQSO
I
Subcode Q data input from the digital signal processor
53
MUTE DSD
O
Muting on/off control signal output to the DSD decoder “H”: muting on (FLX7D only)
54
SQCK
O
Subcode Q data reading clock signal output to the digital signal processor
55
VSS
—
Ground terminal (digital system)
56
TRAY IN
I
Disc tray in detection signal input terminal Not used
57
TRAY OUT
I
Disc tray out detection signal input terminal Not used
58
GFS DVD
I
Guard frame sync signal input from the DVD decoder
59
MUTE CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
60
MUTE 2D
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
61
SLED
I
Sled motor servo drive PWM signal input terminal
62
FG
I
Spindle motor control signal input
63
SP ON
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input from the DVD/CD RF amplifier
66
PI
I
Pull in signal input from the DVD/CD RF amplifier
67
FE
I
Focus error signal input from the DVD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
TSD
O
Thermal shut down signal output to the motor/coil driver
74
FOK CD
I
Focus OK signal input from the digital signal processor
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output “L”: DVD, “H”: SACD (FLX7D only)
78
I2C SIO
I/O
Communication data bus with the DVD system processor and system controller
79
I2C SCL
I/O
Communication data reading clock signal input or transfer clock signal output with the DVD
system processor and system controller
system processor and system controller
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
SDCLK RF
O
Serial data transfer clock signal output to the DVD/CD RF amplifier
83
SDATA RF
I/O
Two-way data bus with the DVD/CD RF amplifier
84
XWR
O
Write strobe signal output to the DVD decoder
85
XRD
O
Read strobe signal output to the DVD decoder
86
(PWE)
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89 to 96
A0 to A7
O
Address signal output to the DVD decoder
97
DSAVE
O
Motor/coil driver power save control signal output terminal Not used
98
XDRST
O
Reset signal output to the digital signal processor and DSD decoder “L”: reset
99
EEP WP
O
Write protect signal output to the EEPROM
100
EEP CLK
O
Clock signal output to the EEPROM
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