Sony DAR-RH1000 / DAR-RH7000 / HCD-RH1000 / HCD-RH7000 Service Manual ▷ View online
HCD-RH1000/RH7000
21
21
HCD-RH1000/RH7000
7-3. BLOCK DIAGRAM – AUDIO Section –
38 RIN2
7 LIN2
EAUAINL1
EAUAINR1
AUDIO INPUT SELECT,
A/D CONVERTER
IC201
M
TULI, TURI, EUAUINL1,
EUAUINR1, EUAUINL3, EUAUINR3
EUAUINR1, EUAUINL3, EUAUINR3
36 RIN1
9
21
LIN1
SDTO
TULI
TURI
3 LIN4
42 RIN4
1 LIN5
EAUAINL3
44 RIN5
EAUAINR3
J702 (2/2)
R
L
LINE 4 IN
AUDIO
J801 (2/2)
R
L
LINE OUT
AUDIO
5 LIN3
40 RIN3
J101 (2/2)
R
L (MONO)
LINE 2 IN
AUDIO
22
BICK
23
LRCK
ATA I/F
IC601 (2/3)
A12
C8
AUIA_DAT
A11 AUIA_BCK
A10 AUIA_LRCK
AUOA_CH12
E11
AUO_DO
B9
AUOA_BVK
N
SCIF2_SDO, SCIF2_SCK, XDSRCS,
XAMUTE, ADMUTE, XSWGBRST
XAMUTE, ADMUTE, XSWGBRST
F
PB_MCK_2, REC_MCK_1
A9
AUOA_LRCK
IT CPU
IC604 (1/3)
107
STR_DATA_OUT
116
STR_DATA_IN
1
STR_CLK
65
STR_CS
64
STR_BUSY
68
STR_MUTE_REQ
67
STR_POW_CNT
66
CN_DET
D/A CONVERTER
IC1402
3
12
SDTI
2 BICK
4 LRCK
AOUTL+
EUAUOUTL
EUAUOUTR
11
AOUTL–
10
AOUTR+
9
AOUTR–
16
DZFL
15
DZFR
AUDIO
OUT AMP
IC301
LVDS
TRANSCEIVER
IC2003
MUTE
Q311
MUTE CONTROL
Q305, 307, 309
MUTE
Q310
L
EUAUOUTL, EUAUOUTR
MUTE CONTROL
Q304, 306, 308
RESET SWITCH
Q315, 316
D304
D303
SPDIF+
SPDIF-
STR_DATA_OUT
STR_DATA_IN
10
11
8
9
STR_CLK
13
STR_BUSY
5
STR_CS
12
STR_MUTE_REQ
3
STR_POW_CONT
7
CN_DET
4
SYSTEM CONNCTER
CN2001
BUFFER
IC2001
8 CDTI
SCIF2_SDO
88 INSEL1
INSEL_1
89 INSEL2
INSEL_2
90 INSELTU
INSEL_TU
95 XP_MUTE
XP_MUTE
48 XFLMRST
XFLMRST5
1 MCLK
PB_MCK_2
7 CCLK
SCIF2_SCK
6 CSN
XDSRCS
5 PDN
XSWGBRST
24
28
MCLK
SEL0
REC_MCK_1
INSEL_1
29
SEL1
INSEL_2
30
SEL2
INSEL_TU
27 SMUTE
ADMUTE
25 PDN
XSWGBRST
XPMUTE
XFLMRST5
XAMUTE
: REC (AUDIO)
SIGNAL PATH
: PB (AUDIO)
(Page 20)
(Page 19)
(Page 25)
(Page 20)
HCD-RH1000/RH7000
22
22
HCD-RH1000/RH7000
7-4. BLOCK DIAGRAM – ATA INTERFACE Section –
DDR_DQ0 – DDR_DQ31
DQ0 – DQ31
AA24, AB25, AC24, AC25, AE24, AC23, AF23,
AD22, AC8, AD8, AB7, AE7, AD5, AF5,AC5, AE4,
AF22, AB22, AC22, AE20, AD20, AC19, AF19, AD18,
AF4, AD4, AB5, AF1, AC2, AB2, AA3, AA4
DDR_SA0 – DDR_SA11
AB15, AD15, AF14,
AC14, AD13, AF11,
AD11, AB11, AF10,
AF12, AF15, AF13
M11 CLK
AC10
DDR_CK
M12 CLK
AF8
DDR_CKN
N12 CKE
AF9
DDR_CKE
N2 CS
AC17
DDR_CS
M2 RAS
AF18
DDR_RAS
L2 CAS
AB18
DDR_CAS
L3 WE
AF17
DDR_WE
B2 DQS0
AF25
DDR_DQS0
H13 DQS1
AF6
DDR_DQS1
H2 DQS2
AF20
DDR_DQS2
B13 DQS3
AD2
DDR_DQS3
B3 DM0
AD26
DDR_DM0
H12 DM1
AC6
DDR_DM1
H3 DM2
AB20
DDR_DM2
B12 DM3
AD1
DDR_DM3
N4 BA0
AC16
DDR_BA0
M5 BA1
AF16
DDR_BA1
N13 VREF
AF24
DDR_VREF0
B7, C6, B6, B5, C2, D3, D2, E2, K13, K12, J13,
J12, G13, G12, F13, F12, F3, F2, G3, G2, J3, J2,
K2, K3, E13, D13, D12, C13, B10, B9, C9, B8
A0 – A7, A8/AP, A9 – A11
N5, N6, M6, N7,
N8, M9, N9, N10,
N11, M8, L6, M7
NAZCA2
IC802 (2/2)
SD-RAM
IC901
SDC_DQ0 – SDC_DQ15
DQ0 – DQ15
C20, D20, B19, D19,
E19, D18, D17, C18
B18, C17, A17, A18,
C16, D16, D15, C15
SDC_SA0 – SDC_SA12
B26, D25, C26,
D24, C25, F22, E23,
H22, G22, D23,
C23, B25 B24
45
CK
A13
S33_CK
SWCPCKB
E10
HST_RD
XCARRD
E9
HST_CS0
XCARCS0
A5
HST_DACK
SWDACK0
E8
HST_CS1
XCARCS1
C5
HST_DREQ
XSWDREQ0
L5
HST_RDY
CARRDY
A6
HST_INT0
B6
HST_INT1
XCARINT1
XCARINT0
E7
HST_WE0
XCARWE0
D7
HST_WE1
XCARWE1
E6
HST_WE2
XCARWE2
D5
HST_WE3
XCARWE3
V1
HST_RD
XNZRRD
R3
HST_WE0
HST_CS
XNAZWE0
W2
HST_DACK
SWDACK1
T3
XNAZCS
XSWDREQ1
HST_DREQ Y2
NAZRDY
HST_RDY Y1
HST_INT W3
T2
HST_WE1
XNAZWE1
R4
HST_WE2
XNAZWE2
T1
HST_WE3
XNAZWE3
XNAZINT
A24 SDC_CK
46
CK
A25 SDC_CKN
44
CKE
A23 SDC_CKE
24
CS
E20 SDC_CS0
23
RAS
A21 SDC_RAS
22
CAS
B22 SDC_CAS
21
WE
A20 SDC_WE
16
LDQS
B21 SDC_DQS0
51
UDQS
B20 SDC_DQS1
20
LDM
D21 SDC_DM0
47
UDM
C21 SDC_DM1
26
BA0
D22 SDC_BA0
27
BA1
E21 SDC_BA1
49
VREF
E17 SDC_VREF0
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
A0 – A9, A10/AP
A11, A12
29 – 32
35 – 40,
28, 41, 42
DDR_DQ0 – DDR_DQ31
DQ0 – DQ31
AB24, AC26, AB25, AA24, AB26, AA25, W23,
Y24, W24, Y26, W25, U23, V24, W26, V25,
U24, U26, R23, T23, R24, R25, P23, P24, R26,
N26, N25, M26, N24, N23, M26, L26, M24
HST_D0 –HST_D31
P3, R1, P2, P1 ,N3, N2, M1, M3,
M2, M4, L2, L3, K1, K2, J1, K3,
J2, H2, J3, H3, J4, G2, H4, G3,
F1, F2, G4, E1, F4, F3, D1, D4
DDR_SA0 – DDR_SA11
M23, K26, K25,
J26, L23, K24,
J25, H26,J24,
K23, H25, H23,
HST_A2 – HST_A25
E3, D3, C1, C2, B3, A2,
C4, B4, B2, A3, D6, A4,
D5, B5, C6, A5, D7, B6,
D8, C7, A6, C9, B7, D9
M11
CLK
V26 DDR_CK
M12
/CLK
U25 DDR_CKN
N12
CKE
F25 DDR_CKE
N2
/CS
G24 DDR_CS
M2
/RAS
G25 DDR_RAS
L2
/CAS
F26 DDR_CAS
L3
/WE
G26 DDR_WE
B2
DQS0
Y25 DDR_DQS0
H13
DQS1
T25 DDR_DQS1
H2
DQS2
P26 DDR_DQS2
B13
DQS3
L25 DDR_DQS3
B3
DM0
E26 DDR_DM0
H12
DM1
F24 DDR_DM1
H3
DM2
E25 DDR_DM2
B12
DM3
F26 DDR_DM3
N4
BA0
E24 DDR_BA0
M5
BA1
F23 DDR_BA1
N13
VREF
R22 DDR_VREF0
B7, C6, B6, B5, C2, D3, D2, E2, K13, K12, J13,
J12, G13, G12, F13, F12, F3, F2, G3, G2, J3, J2,
K2, K3, E13, D13, D12, C13, B10, B9, C9, B8
A0 – A7, A8/AP, A9 – A11
N5, N6, M6, N7,
N8, M9, N9, N10,
N11, M8, L6, M7
ATA I/F
IC601 (3/3)
HST_D0 – HST_D31
A4, A3, A2, B4, B3, B2, B1, C3,
C1, D4, D3, D2, D1, E4, E3, E2,
E1, F5, F4, F3, F2, F1, G5, G4,
G3, G2, H4, H3, H2, H1, J5, J4
HST_A2 – HST_A25
J3, J2, J1, K4, K3, K2,
K1, L4, L3, L2, L1, M4,
M3, M2, N4, N3, N2, N1,
P4, P3, P2, P1, R2, R1
U
SWCPCKB, XCARRD,
XCARWE0 – XCARWE3,
XCARINT0, XCARINT1
T
SWDACK0,
XCARCS0, XCARCS1,
XSWDREQ0, CARRDY
S
XNZRRD,
XNAZWE0 – XNAZWE3,
XNAZINT
R
SWDACK1, XNAZCS,
XNAZCS, NAZRDY
DATA BUS
SWHD0 – SWHD31
P
ADDRESS BUS
SWHA2 – SWHA25
Q
SWHD0 – SWHD31
SWHD0 – SWHD31
SWHA2 – SWHA25
SWHA2 – SWHA25
DATA BUS
ADDRESS BUS
SD-RAM
IC702
SD-RAM
IC701
(Page 24)
(Page 24)
(Page 23)
(Page 24)
(Page 23)
(Page 24)
HCD-RH1000/RH7000
23
23
HCD-RH1000/RH7000
7-5. BLOCK DIAGRAM – MAIN Section (1/3) –
ADDRESS BUS
25
1OE
48
1A1 – 1A8, 2A1 – 2A8
UNHD0 – UNHD15
SHHD0 – SHHD15
1B1 – 1B8, 2B1 – 2B8
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8,
9, 11, 12, 13,
14, 16, 17, 19,
20, 22, 23
2OE
1
1DIR
24
2DIR
32
CE
BUFFER
IC307
DQ0 – DQ15
35, 37, 39, 41,
44, 46, 48, 50,
36, 38, 40, 42,
45, 47, 49, 51
A0 – A22
FLASH MEMORY
IC201
25
1OE
48
1A1 – 1A8, 2A1 – 2A8
UNHD16 – UNHD31
SHHD16 – SHHD31
1B1 – 1B8, 2B1 – 2B8
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8,
9, 11, 12, 13,
14, 16, 17, 19,
20, 22, 23
2OE
1
1DIR
24
2DIR
BUFFER
IC310
1Y1 – 1Y8, 2Y1 – 2Y8
UNHA0 – UNHA15
SHHA0 – SHHA15
1A1 – 1A8, 2A1 – 2A8
2, 3, 5, 6, 8,
9, 11, 12, 13,
14, 16, 17, 19,
20, 22, 23
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
BUFFER
IC308
1Y7, 1Y8, 2Y1 – 2Y8
UNHA16 – UNHA25
SHHA16 – SHHA25
1A7, 1A8, 2A1 – 2A8
11, 12,
13, 14, 16,
17, 19, 20,
22, 23
38, 37,
36, 35, 33,
32, 30, 29,
27, 26
XUNHDGT
VSYNC
UNRW1
BUFFER
IC306
31, 26 – 20,
10 – 3, 54, 19, 20,
11, 12, 15, 2
34
OE
13
WE
14
RESET
32
CE
DQ0 – DQ15
35, 37, 39, 41,
44, 46, 48, 50,
36, 38, 40, 42,
45, 47, 49, 51
A0 – A22
FLASH MEMORY
IC202
XUNWE2
XUNRD1
XUNWE0
XUNRD1
UNHA2 – UNHA24
UNHA2 – UNHA24
UNHD0 – UNHD15
UNHD16 – UNHD31
UNHD0 – UNHD15
UNHD0 – UNDH15
UNHA0 – UNHA5,
UNHA23 – UNHA25
HOST GLUE
IC501
UNHA0 – UNHA5,
UNHA23 – UNHA25
UNHA23 – UNHA25
31, 26 – 20,
10 – 3, 54, 19, 20,
11, 12, 15, 2
34
OE
13
WE
14
RESET
82 – 89, 92 – 99
116 – 111, 125 – 123
B
VSYNC, VDCTRST
X
CONT
Y
XFLMRST3
136
122
XFLMCS0
XUNRD
XFLMCS0
77
SHDACK0
78
SHDACK1
128
XSHCS0
129
XSHCS1
130
XSHCS2
131
XSHCS4
132
XSHCS5
133
XSHCS6
79
XSHDREQ0
80
XSHDREQ1
107
XGPSINT
108
XGPSINT2
106
XSHRDY
100
XUNGBRST
A18
XUNRD2
121 XUNWE0
XUNWE0
120 XUNBS
XUNBS
110 UNRW
UNRW1
118 CLK66
22 XHDMIINT2
37 XMSRST
CPUCK66G
75 PCONT
P_CONT
33 NAZDACK
SWDACK1
5 XNAZCS
XNAZCS
32 XNAZDREQ
XSWDREQ1
26 NAZRDY
NAZRDY
139
XUNHDGT
XUNHDGT
140
XSWHDGT0
3 1Y2
46
1A2
XSWHDGT0
103
XSWGT0
XSWGT0
XSWGT1
104
XSWGT1
R
SWDACK1, XNAZCS,
XNAZCS, NAZRDY
XNAZCS, NAZRDY
10 XCARCS0
XCARCS0
35 CARDACK
SWDACK0
11 XCARCS1
XCARCS1
34 XCARDREQ
XSWDREQ0
27 CARRDY
CARRDY
T
SWDACK0,
XCARCS0, XCARCS1,
XSWDREQ0, CARRDY
XCARCS0, XCARCS1,
XSWDREQ0, CARRDY
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
DATA BUS
DATA BUS
SHHD0 – SHHD31
V
ADDRESS BUS
SHHA0 – SHHA25
W
DATA BUS
ADDRESS BUS
VDCTRST
DACK0
D19 DCAK1
F3 CS0
H1
J3
K2
N1
P2
E19
E20
M19
J2
C1
B14
CS1
CS2
CS4
CS5
CS6
DREQ0
DREQ1
IRL3
XGPSINT2
RDY
XUNGBRST
XFLMCS0
SYSTEM CONTROL
IC104 (1/3)
(Page 22)
(Page 22)
(Page 24)
(Page 24)
(Page 19)
(Page 24)
(Page 25)
HCD-RH1000/RH7000
24
24
HCD-RH1000/RH7000
7-6. BLOCK DIAGRAM – MAIN Section (2/3) –
25
1OE
48
1A1 – 1A8, 2A1 – 2A8
SWHD0 – SWHD15
SHHD0 – SHHD15
1B1 – 1B8, 2B1 – 2B8
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8,
9, 11, 12, 13,
14, 16, 17, 19,
20, 22, 23
2OE
1
1DIR
24
2DIR
BUFFER
IC302
25
1OE
48
1A1 – 1A8, 2A1 – 2A8
SWHD16 – SWHD31
SHHD16 – SHHD31
1B1 – 1B8, 2B1 – 2B8
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8,
9, 11, 12, 13,
14, 16, 17, 19,
20, 22, 23
2OE
1
1DIR
24
2DIR
BUFFER
IC304
1
1OE1
24
1Y3 – 1Y8, 2Y1 – 2Y8
SWHA2 – SWHA15
SHHA0 – SHHA15
1A1 – 1A8, 2A1 – 2A8
5, 6, 8, 9, 11,
12, 13, 14,
16, 17, 19,
20, 22, 23
47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,
30, 29, 27, 26
2OE1
48
1OE2
25
2OE2
BUFFER
IC303
DATA BUS
SWHD0 – SWHD31
P
ADDRESS BUS
DATA BUS
DATA BUS
DATA BUS
DATA BUS
ADDRESS BUS
SWHA2 – SWHA25
Q
DATA BUS
SHHD0 – SHHD31
V
ADDRESS BUS
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
SHHA0 – SHHA25
W
1
1OE1
24
1Y1 – 1Y8, 2Y1, 2Y2
SWHA16 – SWHA25
SHHA16 – SHHA25
1A1 – 1A8, 2A1, 2A2
2, 3, 5,
6, 8, 9,
11, 12,
13, 14
47, 46,
44, 43, 41,
40, 38, 37,
36, 35
2OE1
48
1OE2
25
2OE2
BUFFER
IC305
19
CS
38
CLK
DQ0 – DQ15
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
A0 – A12, BA0, BA1
SD-RAM
IC108
23 – 26,
29 – 34, 22, 35,
36, 20, 21
18
RAS
17
CAS
16
WE
XSHRD
XSHCS3
37
CKE
CKE
XSHRAS
SHRW
15
DQML
XSHWE0
39
DQMU
XSHWE1
SHHA2 – SHHA16
SYSTEM CONTROL
IC104 (2/3)
Y10 CLKIO
3 1Y0
2 1Y1
5 1Y2
7 1Y3
1
CLKIN
BUFFER
IC110
22 2Y7
SWCPCKB
20 2Y6
19 2Y5
17 2Y4
27
2A7
30
2A5
32
2A4
BUFFER
IC301
29
2A6
35
2A2
36
2A1
XSHWE3
37
1A8
38
1A7
XSHWE2
40
1A6
41
1A5
XSHWE1
43
1A4
44
1A3
XSHWE0
XSWGT1
XSHRD
CPUCK66G
Y6 RD
XSHRD
XNZCRD
XCARRD
14 2Y2
XNAZWE3
13 2Y1
XCARWE3
12 1Y8
XNAZWE2
11 1Y7
XCARWE2
9 1Y6
XNAZWE1
8 1Y5
XCARWE1
6 1Y4
XNAZWE0
5 1Y3
XCARWE0
1
1OE1
24
2OE1
48
1OE2
25
2OE2
20 2Y6
19 2Y5
17 2Y4
30
2A5
32
2A4
BUFFER
IC309
29
2A6
XSHWE0
XSHWE2
37
1A8
38
1A7
SHRW
23 2Y8
UNRW1
26
2A8
XUNWE2
XUNWE0
12 1Y8
XUNRD1
11 1Y7
XUNRD2
44
1A3
XSHBS
5 1Y3
XUNBS
XSHRD
W6 RD/WR
SHRW
W7 WE0
XSHWE0
Y7 WE1
XSHWE1
W14 WE2
XSHWE2
Y14 WE3
XSHWE3
R2 BS
XSHBS
XCARINT0
N20 IRL0
XCARINT1
N19 IRL1
XANZINT
M20 IRL2
P_CONT
D4 P_CONT
D0 – D31
SHHD0 – SHHD31
U2, V2, W1, U3, W3, Y3, W4, W5, Y5,
Y4, V4, T3, Y2, Y1, V1, U1, U19, V19,
Y20, Y19, U17, V17, Y17, Y16, W16,
W17, Y18, W18, U18, W20, V20, U20
SHHD0 – SHHD15
19
CS
38
CLK
DQ0 – DQ15
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
A0 – A12, BA0, BA1
SD-RAM
IC109
23 – 26,
29 – 34, 22, 35,
36, 20, 21
18
RAS
17
CAS
16
WE
XSHRD
XSHCS3
XSHRAS
SHRW
15
DQML
XSHWE2
39
DQMU
XSHWE3
SHHA2 – SHHA16
SHHD16 – SHHD31
A0 – A25
SHHA0 – SHHA25
R4, R1, V6, Y8, W8, Y9, W9, V9,
W10, Y11, W11, Y12, W12, Y13,
W13, V13, V15, U9, U13, U15,
L4, M3, T17, T18, R17, R18
XSWHDGT0
XSWGT0
S
CONT
U
XNZRRD,
XNAZWE0 – XNAZWE3,
XNAZINT
XNAZWE0 – XNAZWE3,
XNAZINT
SWCPCKB, XCARRD,
XCARWE0 – XCARWE3,
XCARINT0, XCARINT1
XCARWE0 – XCARWE3,
XCARINT0, XCARINT1
X
Y15 CS3
XSHCS3
U6 CKE
CKE
W14 RAS
XSHRAS
37
CKE
CKE
SWITCHING
IC106
Z
P_CONT
(Page 23)
(Page 23)
(Page 22)
(Page 22)
(Page 22)
(Page 22)
(Page 23)
(Page 26)
Click on the first or last page to see other DAR-RH1000 / DAR-RH7000 / HCD-RH1000 / HCD-RH7000 service manuals if exist.