DOWNLOAD Sony BDV-E500W / HCD-E500W Service Manual ↓ Size: 6.33 MB | Pages: 126 in PDF or view online for FREE

Model
BDV-E500W HCD-E500W
Pages
126
Size
6.33 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
bdv-e500w-hcd-e500w.pdf
Date

Sony BDV-E500W / HCD-E500W Service Manual ▷ View online

HCD-E500W
HCD-E500W
21
21
SECTION  4
ELECTRICAL  CHECK
FM  TUNER  LEVEL  CHECK
Procedure:
1.  Turn on the set.
2.  Input the following signal from Signal Generator to FM antenna 
input directly.
Carrier frequency : A = 87.5 MHz, B = 98 MHz, C = 108 MHz
Deviation 
: 75 kHz
Modulation 
: 1 kHz
ANT input 
: 35 dBu (EMF)
Note: Use 75 ohm coaxial cable to connect signal generator and the set. 
You cannot use video cable for checking.
 
Use signal generator whose output impedance is 75 ohm.
3.  Set to FM tuner function and tune A, B and C signals.
4. Confi rm “TUNED” is lit on the display for A, B and C signals.
When the selected station signal is received in good condi-
tion, “TUNED” is displayed.
signal 
generator
set
4.  CONFIRMATION  ITEM
4-1.  Playback Operation Confi rmation
4-1-1. Test Disc
Part No.
Description
Layer
J-6090-199-A
BLX-104
Single Layer
J-6090-200-A
BLX-204
Dual Layer
3-702-101-01
CD (YEDS-18)
J-6090-088-A
HLX-504
Single Layer (NTSC)
J-6090-089-A
HLX-505
Dual Layer (NTSC)
J-6090-077-A
HLX-506
Single Layer (PAL)
J-6090-078-A
HLX-507
Dual Layer (PAL)
Note: Refer to the service manual of BDP-BX1/S350 (Part No. 9-883-
989-1[]) (page 1-3 to 1-14E) for the use of BLX-104/204.
Operation and Display:
1. BLX-104
Procedure:
1. Select 
23.976Hz/1080p.
2.  Play “4.Motion picture”.
3.  Check whether player can play back or not.
4.  Check each outputs.
 Video:
 Composite/S 
Video/component/HDMI.
 Audio:
 Speaker 
out.
*  When 1080/24p monitor is nothing, 1080i (59.94Hz or 50Hz) 
can use instead of 1080/24p.
 
However this is temporary correspondence.
*  When the output of HDMI is 1080p, the signal of Composite/S 
Video/Component are not output.
 
It is necessary to lower the output of HDMI to 1080i or less.
2. BLX-204
Procedure:
1.  Select 1080i (59.94Hz or 50Hz).
2.  Play “4.Motion picture”.
3.  Check whether player can play back or not.
 
(Check the picture and sound output)
3. CD (YEDS-18)
Procedure:
Check whether player can play back or not.
(Check the sound output)
4.  HLX-504/505 (NTSC), HLX-506/507 (PAL)
Procedure:
1.  After displayed Main Menu, select “1.Video Signal”.
2.  Play “1.Color bar 100%”.
 
(Check the picture and sound output)
3.  Return to Menu.
4.  Play “Demonstration 4:3” or “Demonstration 16:9”.
 
(Check the picture and sound output)
4-1-2.  Playback operation confi rmation
Confi rm operation in each signal/output mode of test disc (BLX-
104/204) according to the content of the repair.
Note: “AV Sync.” doesn’t operate.
4-2. Networking Confi rmation
Confi rm it according to the following procedure when you confi rm 
the connection of the network.
Note: Do not execute “Network Diagnostic” of “Set up” of the home 
menu with only the router connected.
Procedure:
1.  Connect the router with the set with LAN cable.
2.  Turn on the power of the set and the router.
3.  Press the [HOME] button on the remote commander, and the 
home menu is displayed.
4.  Select “Set up” 
→ “Network Settings” → “Internet Settings”, 
and press the [3] button on the remote commander.
5. Confi rm “Use DHCP” is displayed in “IP Address Acquisi-
tion”, and confi rm IP address are displayed in “IP Address”, 
“Subnet Mask” and “Default Gateway”.
Internet Settings
IP Address Acquisition
Use DHCP
IP Address
XXX.XXX.XXX.XXX
DNS Server Acquisition
Auto Acquisition
DNS Server (Primary)
XXX.XXX.XXX.XXX
Subnet Mask
XXX.XXX.XXX.XXX
Default Gateway
XXX.XXX.XXX.XXX
Ver. 1.1
HCD-E500W
HCD-E500W
22
22
SECTION  5
DIAGRAMS
5-1.  BLOCK  DIAGRAM - BD Section -
X600
33MHz
X8001
50MHz
BD DRIVE
(BPD-200)
SARXP0
A23
HR+0
SARXN0
B23
HR-0
SATXP0
B21
HT+0
SATXN0
A21
HT-0
‡ SI*NA/ PATH
: AUDIO
: VIDEO
: BD/DVD
: USB
: /AN
DDR2 SD-RAM
IC102
UMWEB
UMA0 - UMA12,
UMA14, UMA15
UMDQ0 - UMDQ15
UMCSB0
R5
AA2
K3
/8
/WE
UMBA0
U5
/2
BA0
UMBA1
V2
/3
BA1
UMCSB1
AA6
/1
BA2
/CS
UMCASB
UMRASB
Y6
AA4
/
K
/CAS
/RAS
UMCKE
V5
K2
CKE
UMCK0
M1
J8
CK
UMCKB0
N1
K8
/CK
UMDM1
UMDQS1
N3
J1
B3
B
UDM
UDQS
UMDQSB1
UMDM0
K1
U2
A8
F3
/UDQS
/DM
UMODT0
AB1
K9
ODT
UMDQS0
R1
F
/DQS
UMDQSB0
T1
E8
//DQS
A0 - A12
DQ0 - DQ15
DDR2 SD-RAM
IC103
UMDQ16 - UMDQ31
K3
/8
/WE
/2
BA0
/3
BA1
/1
BA2
/CS
/
K
/CAS
/RAS
K2
CKE
UMCK1
A*1
J8
CK
UMCKB1
AH1
K8
/CK
UMDM3
UMDQS3
AJ2
AK1
B3
B
UDM
UDQS
UMDQSB3
UMDM2
A/1
AD3
A8
F3
/UDQS
/DM
K9
ODT
UMDQS2
AD1
F
/DQS
UMDQSB2
AE1
E8
//DQS
A0 - A12
DQ0 - DQ15
DDR2 SD-RAM
IC202
WMWEB
WMA0 - WMA12,
WMA14, WMA15
WMDQ0 - WMDQ15
WMCSB0
AJ19
AM13
K3
/8
/WE
WMBA0
AJ1
/2
BA0
WMBA1
AM16
/3
BA1
WMCSB1
AH13
/1
BA2
/CS
WMCASB
WMRASB
AH14
AK13
/
K
/CAS
/RAS
WMCKE
AJ16
K2
CKE
WMCK0
AN21
J8
CK
WMCKB0
AN22
K8
/CK
WMDM1
WMDQS1
A/21
AN24
B3
B
UDM
UDQS
WMDQSB1
WMDM0
AN25
AM1
A8
F3
/UDQS
/DM
WMODT0
AN12
K9
ODT
WMDQS0
AN18
F
/DQS
WMDQSB0
AN19
E8
//DQS
A0 - A12
DQ0 - DQ15
DDR2 SD-RAM
IC203
WMDQ16 - WMDQ31
K3
/8
/WE
/2
BA0
/3
BA1
/1
BA2
/CS
/
K
/CAS
/RAS
K2
CKE
WMCK1
AN6
J8
CK
WMCKB1
AN
K8
/CK
WMDM3
WMDQS3
AM5
AN3
B3
B
UDM
UDQS
WMDQSB3
WMDM2
AN4
A/10
A8
F3
/UDQS
/DM
K9
ODT
WMDQS2
AN9
F
/DQS
WMDQSB2
AN10
E8
//DQS
A0 - A12
DQ0 - DQ15
4M NOR F/ASH ROM
IC501
C/OCK *ENERATOR
IC00
BD DECODER
IC101
RADD1 - RADD18
RDATA0 - RDATA15
FWEB
AK28
11
28
WE
SACREFP
B15
SSC/K
OE
FOEB
AK26
26
CE
FCSB0
AJ25
12
RESET
A0 - A1
DQ0 - DQ15
2* NAND F/ASH ROM
IC502
EMI_DT0 -
EMI_DT
EMI_DT0 -
EMI_DT15
D1MA0 - D1MA3,
D1MA6 - D1MA12,
D1MA14, D1MA15
D0MA0 - D0MA3,
D0MA6 - D0MA12,
D0MA14, D0MA15
D1MA0 - D1MA12
D0MA0 - D0MA12
NWEB
AM26
18
XWE
NFOEB
AN2
8
nRE
FCSB1
NRBB
AK2
AM2
9
nCE
RY/XBY
NA/E
NC/E
A/26
A/2
1
16
A/E
C/E
*PIO13
C26
19
XWP
IO1 - IO8
X401
2MHz
SYSXO
SYSXI
*1
F1
X01
25MHz
XOUT
XIN/C/KIN
2
3
DP2
106
DM2
105
USB INTERFACE
IC602
AD0 - AD31
PCIAD0 - PCIAD31
U_AD24
U_AD31
IDSE/ 29
CN600
EXTERNA/
3
2
CN8001
/AN (100)
X601
30MHz
XT2
XT1/SC/K
83
81
PCICBEB0
F8
PCICBEB1
E
PCICBEB2
E5
PCICBEB3
F5
PCIPAR
B6
CBE00 68
CBE10 55
CBE20 42
CBE30 28
PAR 53
PCIIDSE/
F4
PCISERRB
C6
PCIPERRB
D6
PCISTOPB
E6
PCIDEVSE/B
F6
PCITRDYB
A5
SERR0 52
PERR0 51
STOP0 50
DEVSE/0 49
TRDY0 4
PCIIRDYB
B5
IRDY0 44
PCIF/AMEB
C5
PCIREQB0
F3
FRAME0 43
REQ0 16
PCI*NT0
E2
*PIO30
F21
*NT0
ETHERNET INTERFACE
IC8001
TXD0
23
ETTXD0 AB29
TXD1
24
RXD0
18
RXD1
1
RX_ER
21
TX_EN
6
ETTXD1 AB28
ETRXD0 AA28
ETRXD1 AA29
6
TXN 28
5
2
1
TXP 29
RXN 31
RXP 32
REFC/K 14
ETRXER AA2
ETTXEN AB30
MDIO
4
ETMDIO Y29
MDC
2
nRST
5
ETMDC Y28
CRS_DV
36
ETCRS AA30
ETREFC/K Y30
15
INTA0 14
*PIO9
B2
VBBRST0 13
TX0P Y33
TX0N Y32
TX1P V33
TX1N V32
TX2P T33
TX2N T32
TXCP AB33
TXCN AB32
HDSDA Y31
HDSC/ W31
HHPD
*PIO19 B26
FORMAT1
UA1DTRB J32
USB_VBUS_PCONT
*PIO1 F24
XMUTE
AO0/RCK D32
AO0/RCK
AO0BCK C32
AO0BCK
AO0MCK D33
AO0MCK
ATX B32
SPDIF
AO0BD3 D31
SI_F
AO0BD2 E31
SI_E
AO0BD0 C33
SI_C
AO0BD1 E30
SI_D
S2DOUT F30
S2DIN *32
S2CKIN *29
H2CSB H29
UA0DSRB K29
*PIO14 A2
IF_SDI
CEC
IF_SDO
IF_SCK
XIF_CS
IF_START_BIT
SYSCON_REQ
TEMP
AA31
PCIC/KI
H3
PCIRSTB
XIF_RST
H5
RSTSWB J28
PC/K 11
BUFFER
IC901
BUFFER
IC504
TH901
BUFFER
IC02
VAY
SD_Y
M31
BUFFER
Q803
VAC
SD_C
M33
BUFFER
Q805
VAR
HD_PR
P29
BUFFER
Q801
VA*
HD_Y
P33
BUFFER
Q804
VAB
HD_PB
P31
BUFFER
Q806
/EVE/ SHIFT
Q01
BUFFER
Q901
D
A
C
B
TMDS DATA2 +
TMDS DATA2–
TMDS DATA1+
TMDS DATA1–
TMDS DATA0+
TMDS DATA0–
TMDS C/OCK+
TMDS C/OCK–
CEC
SC/
SDA
HPD
1
3
4
6

9
10
12
15
16
19
13
CN02
HDMI
OUT
(Page 23)
(Page 24)
(Page 27)
(Page 23)
HCD-E500W
HCD-E500W
23
23
5-2.  BLOCK  DIAGRAM - INPUT/OUTPUT Section -
‡6,*1$/3$7+
$8',2
781(5
0,&
9,'(2
Q673
(2/2)
1 Y0
5 Y1
10
$
$8',26(/(&7
,&603
$8',26(/(&7
,&605
3
Y
,/2(;3$1'(5
,&500
,/2(;3$1'(5
,&500
4 Y3
$8/
5 Y1
1 Y0
9
B
3
Y
6$,5/
2 Y2
5&+
/
5
79$8',2,1
J671
$8',2$8',2,1
$&$/0,&
(&0$&2
/
5
5&+
Q672
(1/2)
Q605
10
$
Q673
(1/2)
Q670
J670
0,&$03
,&670
&1900
'03257
13
14
5&+
5
6
7
17
/FK
5FK
5;'
7;'
'(7
9,'(2
/,1($03
,&900
9,'(2$03
,&103
)075
:
&2$;,$/
$0
$17(11$
781(5()0/$0)
/&+
'2
&(
781('
',
&/
5&+
5&+
J100
3
B
/&
B
3
5
/&
5
Y
&20321(17
9,'(2287
26
96$*
19
&Y6$*
15
&5287
Y&0,;
087(
2
20
&Y287
17
&B287
9,'(2$03
,&101
Y,1
&,1
&5,1
1
12
6'/+'
11
&Y,1
&B,1
8
10
5
9,1
3
$6(/
0
5
$6(/
2
7
$6(/
1
6
$6(/
4
11
Q672
(2/2)
$6(/
3
8
96(/
2
20
96(/
1
19
5(6(7B
',1
26
&/.
3
/$7&+
4
,2B', 82
,2B5(6(7 81
,2B&/. 83
,2B&( 80
6Y67(0&21752//(5
,&501(1/6)
67B&(
88
67B&/.
85
67B'2
86
67B',
87
'0325
7B7;'
48
'0325
7B5;'
47
781('
84
)250$71
6'BY
25
9287
6'B&
+'B35
+'BY
+'B3B
$
+
*
J
/
$&$/B6:/'03B'(7
F
13
087(
1
96(/
0
18
2
4
J101
9,'(2287
5FKLVRPLWWHGGXHWRVDPHDV/FK
B'B5(6(7
39
08/
7,B3&0
9
',5B567
22
'63B5(6(7
21
087(B6:
10
16B,1,7
12
;,FB567
08/
7,B3&0
',5B567
'63B5(6(7
087(B6:
,1,7
,FB6',
,FB6'2
,FB6&.
;,FB&6
,FB67$57BB,7
6Y6&21B5(Q
7(03
&(&
'
B'B6'2
32
B'B6',
31
B'B6&/.
33
B'B&6
37
B'B7(03
90
B'B,FB67$57
34
B'B,FB5(Q
36
28 &(&B287
&(&'$7$
6:,7&+
Q500503507
3 &(&B,1
1 Y0
2 Y2
5 Y1
9
B
$8',26(/(&7
,&602
3
Y
10
$
2
.
6$,5B$'&B6(/
24
6$,5B$'&B6(/
(Page 25)
(Page 
22)
(Page 22)
(Page 24)
(Page 25)
(Page 26)
(Page 25)
(Page 24)
HCD-E500W
HCD-E500W
24
24
5-3.  BLOCK  DIAGRAM - DSP Section -
AO0MCK
AO0BCK
AO0LRCK
OPTICAL
RECEIVER
IC600
J600
TV
OPTICAL
DIGITAL IN
SAT/CABLE
COAXIAL
DIGITAL IN
DSP
IC5001
AXR0[10]
/AXR1[3]
130
AXR0[11]
/AXR1[2]
131
AXR0[12]
/AXR1[1]
134
AXR0[13]
/AXR1[0]
135
AXR0[14]
/AXR2[1]
137
AXR0[15]
/AXR2[0]
138
AXR0[0] 113
AXR0[1] 115
AXR0[3] 117
ACLKX0 142
126
ACLKX1 7
SPI0_SOMI/I2C0_SDA
AXR0[8]/AXR1[5]/
SPI1_SOMI
2
SO
5
SI
6
SCK
111
DSP_MISO
SPI0_SIMO
110
DSP_MOSI
SPI0_CLK/I2C0_SCL
108
DSP_SPICLK
SPI0_SCS#/I2C1_SCL
6
107
DSP_SPIDS
7
HOLD#
1
CE#
65
DSP_SF_HOLD
SPI0_ENA#/I2C1_SDA
5 7 61 21 25
105
DSP_SPIENA
AXR0[6]/SPI1_ENA#
121
DSP_INTR
MUTE_SW
DSP_RESET
DIR_RST
RESET#
MULTI_PCM
14
SERIAL FLASH
IC5003
SYSTEM CONTROLLER
IC501 (2/6)
AFSX0 144
AFSX1
EM_D[0] –
EM_D[15]
11
EM_CLK
EM_A[0] –
EM_A[11]
EM_CKE
EM_CS[0]#
EM_RAS#
EM_CAS#
EM_WE#
EM_BA[0]
EM_BA[1]
EM_WE_DQM[0]
EM_WE_DQM[1]
70
71
97
98
37
38
96
94
39
67
OSCIN
23
OSCOUT
24
X5001
25MHz
AU-L
G
B
SPDIF
SI_C
XMUTE
SI_E
SI_F
SI_D
M
SHIFT
SCDT
DSP_LRCK
MCK
DSP_BCK
AMP_D3
AMP_D1
AXR0[2] 116
S-AIR_D1
S-AIR_D2
S-AIR_D3
S-AIR_BCK
S-AIR_LRCK
8 RX4
10 RX6
21
RDATA
17
RBCK
20
RLRCK
16
RMCK
33
AUDIO
DIGITAL AUDIO
INTERFACE RECEIVER
IC702
39
CE
37
DO
36
RERR
72
DIR_RERR
100
DIR_HDOUT
DAMP_SCDT/DIR_DIN
DAMP_SHIFT/DIR_CLK
76
DIR_HCE
18
DIR_DA
TA0
DIR_AUDIO
41
XMODE
40
CL
38
DI
3 RX1
XIN
XOUT
29
D701
28
X700
24.576MHz
Q700
34
CKST
75
DIR_CKST
1 2
R-CH
13 VinL
VinR
BCK
LRCK
SCKI
14
8
7
6
A/D CONVERTER
IC700
DOUT 9
38
BUFFER
IC701
CLOCK
BUFFER
IC706, 707,
Q701
DATA SELECT
IC703
14
5
6
2
3
4A
2B
2A
1B
1A
12
1
7
4
4Y
SEL
2Y
MUTING CONTROL
IC709
2
1 A
B
6
5
A/B
Y
1Y
11
10 3B
3A
9
3Y
J
N
‡ SIGNAL PATH
: AUDIO
R-ch is omitted due to same as L-ch.
AXR0[5]
/SPI1_SCS#
120
AXR0[7]/SPI1_CLK
122
AHCLIO0/
AHCLKX2
2
ACLKR0
139
ACLKR1
9
AFSR0
141
AFSR1
12
SD-RAM
IC5002
CLK
DQ0 – DQ15
A0 – A11
38
CKE
37
CS#
19
RAS#
18
CAS#
17
WE#
16
BA0
20
BA1
21
LDQM
15
UDQM
39
(Page 23)
(Page 22)
(Page 23)
(Page 
26)
(Page 
25)
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