Sharp LC-37AD1E (serv.man10) Service Manual ▷ View online
61
61-1
61-2
LC-37AD1E
Ë
HISDA5550M-1Y (ASSY:IC1601)
Teletext CPU
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
99,1,3,4,2,100,
D0-D7
I/O
Data bus for external memory or data RAM.
98,96
97,94,93,89,86,84,
A0-A16
O
Address bus for external program memory or data RAM.
82,79,81,83,90,85,
77,78,76,71,69
70,68,67
A17-A19/
I/O
After power-on P4.0,P4.1,P4.4 work as additional address lines A17
···
19.
P4.0,P4.1,P4.4
In port mode, these port lines act as bi-directional I/O port with internal pull-up
resistors. Port pins that have '1' written to them are pulled high by the internal
pull-up resistors and in that state can be used as inputs.
9,10,11,12,13,14,
P0.0-P0.7
I/O
Port 0 is a 8-bit open drain bi-directional I/O-port. Port 0 pins that have 1
15,16
written to them float: in this state they can be used as high impedance inputs.
41,42,43,44,45,46,
P1.0-P1.7
I/O
Port is a 8-bit bi-directional multifunction I/O port with internal pull-up resistors.
47,62
(PWM)
Port 1 pins that have 1 written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
The secondary functions of port 1 pins are:
Port bits P1.0-P1.5 contain the 6 output channels of the 8-bit pulse width
modulation unit.
Port bits P1.6-P1.7 contain the two output channels of the 14-bit pulse width
modulation unit.
24,25,26,27
P2.0-P2.3
I
Port 2 is a 4-bit input port without pull-up resistors.
(ADC)
Port 2 also works as analog input for the 4-channel-ADC.
31,32,33,34,35,36,
P3.0-P3.7
I/O
Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins
37,38
that have 1 written to them are pulled high by the internal pull-up resistors and in
that state can be used as inputs,
To use the secondary functions of Port 3, the corresponding output latch must
be programmed to a one (1) for that function to operate. The secondary
functions are as follows:
· Alternate function
P3.0: ODD/EVEN indicate output
P3.1: external extra interrupt 0(INTX0)/UART(TXD)
P3.2: interrupt 0 input/timer 0 gate control input)INT0)
P3.3: interrupt 1 input/timer 1 gate control input)INT1)
P3.4: counter 0 input(T0)
P3.5: counter 1 input(T1) or In master mode HS or VCS output.
P3.7: external extra interrupt 0(INTX1)/UART(RXD)
48,49
P4.2-P4.3(P4.7)
I/O
Port 4 is a bi-directional I/O port with internal pull-up resistors.
Port 4 pins that have 1 written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
Secondary functions
P4.2: RD, Read line. This signal is same as the to output of the pin RD available
in some packages.
P4.3: WR write line. This signal is same as the output of the pin WE, which is
only available in some package.
5
XROM
I
This pin must be pulled low to access external ROM.
17
ENE
I
Enable Emulation
Only if this pin set to zero externally, STOP and OCF are operational. ENE has
an internal pull-up resistor which switches automatically to non-emulation mode
if ENE is not connected.
18
STOP
I
STOP
Emulation control line; Driving a low level during the input phase freezes the real
time relevant internal peripherals such as timers and interrupt controller.
19
OCF
O
Opcode Fetch
Emulation control line; A high level driven by the controller during output phase
indicates the beginning of a new instruction.
20
EXTIF
21
CVBS
I
CVBS input for the acquisition circuit.
29
HS/SC
I
In slave mode Horizontal sync input or sandcastle input for display
synchronization .In master mode HS or VCS output.
30
VS/P4.7
I/O
Vertical sync input/output for display synchronization.
Can also be used as digital input P4.7.
Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to
P3.0.
50
RST
I
A
low level on this pin resets the device. An internal pull-up resistor permits
power-on reset using only one external capacitor connected to Vss.
62
62-1
62-2
LC-37AD1E
Pin No
.
Pin Name
I/O
Pin Function
52
XTAL2
O
Output of the inverting oscillator amplifier.
53
XTAL1
I
Input of the inverting oscillator amplifier.
57
R
O
Red
58
G
O
Green
59
B
O
Blue
60
BLANK/COR
O
Contrast reduction and blanking.
64
WR
O
Control output; indicates a write access to the internal XRAM; can be used as a
write strobe for writing data into an external data RAM by a MOVX instruction.
This signal is also available as P4.3.
65
RD
O
Control output; indicates a read access to the internal XRAM; can be used for
latching data from the data bus into an external data RAM by a MOVX
instruction.
This signal is also available as P4.2.
72
FL_PGM
I
All the pins prefix by Flax are test pins which must be left open.
80
FL_RST
I
All the pins prefix by Flax are test pins which must be left open.
87
ALE
O
Address Latch Enable.
88
PSEN
O
Program Store Enable
is a control output signal which is usually connected to OE input line of the
external program memory to enable the data output.
95
FL_CE
I
All the pins prefix by Flax are test pins which must be left open.
6,73
VDD2.5
—
Supply voltage (2.5V).
22,56
VDDA2.5
—
Supply voltage for analog components (2.5V).
8,40,75,92
VDD3.3
—
Input/output (3.3V).
7,39,74,91,
VSS
—
Ground (0V).
23,55
VSSA
—
Ground for analog components.
28,51,54,61,63,66
——
Ë
HI62S8308X-1Q(ASSY:IC1603)
256K X 8-bit Low Voltage CMOS SRAM
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1-4,7,
A0-A17
I
A
ddress Inputs
9-20,31
5
W
E
I
Write Enable
6
CE2
I
C
hip Enable2
8
VCC
—
Device Power Supply
21-23,
I/O0-I/O7
I/O
Data Inputs/Outputs
25-29
24
GND
—
Ground
30
CE1
I
Chip Enable1
32
OE
O
Output Enable
63
63-1
63-2
LC-37AD1E
Ë
VHINJU26106-1Q(ASSY:IC2521)
DOLBY PROLOGIC
II
/VIRTUAL DOLBY SURROUND
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1
TEST0
O
Sound data output CH2
2
TEST1
O
Sound data output CH1
3
SDO0
O
Sound data output CH0
4
SEL1
I
I2C(="L"),serial(="H") setup
5
SCL/SCK
I
I2C clock / serial clock
6
SDA/SDOUT
I/O
I2C I/O / serial out
7
AD1/SDIN
I
I2C address / serial in
8
AD2/SSX
I
I2C address / serial enable
9
VDDO
—
Power supply for oscillator (+2.5V)
10
XI
I
C
lock input terminal
11
XO
O
Output for VCO connection
12
VSSO
—
Oscillator power supply GND
13
RESETX
I
Reset
14
VDDC
—
Internal power supply +2.5V
15
VSSC
—
Internal power supply GND
16
TEST2
I/O
When using it, it connects with open.
17
VDDC
—
Internal power supply +2.5V
18
VDDC
—
Internal power supply +2.5V
19
VSSC
—
Internal power supply GND
20
VSSC
—
Internal power supply GND
21
VDDR
—
Power supply for I/O (+2.5V)
22
VDDR
—
Power supply for I/O (+2.5V)
23
VSSR
—
I/O ground
24
VSSR
—
I/O ground
25
SDI0
I
Sound data input 0
26
SDI1
I
Sound data input 1
27
TEST3
I
W
hen using it, it connects with GND.
28
LRI
I
LR clock input
29
BCKI
I
B
it clock input
30
MCK
O
A
/D, D/A clock output
31
BCKO
O
B
it clock output
32
LRO
O
LR clock output
Ë
RH-IXA134WJN4Q(ASSY:IC1602)
8M(1M X 8/512k X 16)bit Dual opration flash memory
»
Block Diagram
Pin No
.
P
in Name
I/O
Pin Function
»
Pin Function
1-8,
A-1, A0-A17
I
Address Inputs
17-25,45
29-36,
DQ0-DQ15
I/O
Data Inputs/Outputs
38-45
26
CE
I
Chip Enable
28
OE
O
Output Enable
11
WE
I
W
rite Enable
12
RESET
I
Hardware reset
15
RY/BY
O
Ready/busy Output
64
64-1
64-2
LC-37AD1E
Ë
RH-IXA416WJZZQ (ASSY:IC2501)
Multi Standard Sound Processor
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1N
C
—
Not connected
2
I2C_CL
I/O
I2C clock
3
I2C_DA
I/O
I2C data
4
I2S_CL
I/O
I2S clock
5
I2S_WS
I/O
I2S word strobe
6
I2S_DA_OUT
O
I2S data output
7
I2S_DA_IN1
I
I2S1 data input
8
ADR_DA
O
ADR data output
9
ADR_WS
O
ADR word strobe
10
ADR_CL
O
ADR clock
11,12,13
DVSUP
—
Digital power supply 5V
14,15,16
DVSS
—
Digital ground
17
I2S_DA_IN2
I
I2S2-data input
18
NC
—
Not connected
19
I2S_CL3
I
I2S3 clock
20
I2S_WS3
I
I2S3 word strobs
21
RESETQ
I
Power-on-reset
22
I2S_DA_IN3
I
I2S3-data input
23
NC
—
Not connected
24
DACA_R
O
Headphone out, right
25
DACA_L
O
Headphone out, left
26
VREF2
—
Reference ground 2
27
DACM_R
O
Loudspeaker out, right
28
DACM_L
O
Loudspeaker out, left
29,31,32
NC
—
Not connected
30
DACM_SUB
O
Sub woofer output
33
SC2_OUT_R
O
SCART 2 output, right
34
SC2_OUT_L
O
SCART 2 output, left
35
VREF1
—
Reference ground 1
36
SC1_OUT_R
O
SCART 1 output, right
37
SC1_OUT_L
O
SCART 1 output, left
38
CAPL_A
—
Volume capacitor AUX
39
AHVSUP
—
Analog power supply 8V
40
CAPL_M
—
Volume capacitor MAIN
41,42
NC
—
Not connected
43,44
AHVSS
—
Analog ground
45
AGNDC
—
Analog reference voltage
46
NC
—
Not connected
47
SC4_IN_L
I
SCART 4 input, left
48
SC4_IN_R
I
SCART 4 input, right
49
ASG
—
Analog Shield Ground
50
SC3_IN_L
I
SCART 3 input, left
51
SC3_IN_R
I
SCART 3 input, right
52
ASG
—
Analog Shield Ground
53
SC2_IN_L
I
SCART 2 input, left
54
SC2_IN_R
I
SCART 2 input, right
55
ASG
—
Analog Shield Ground
56
SC1_IN_L
I
SCART 1 input, left
57
SC1_IN_R
I
SCART 1 input, right
58
NC
—
Not connected
59
VREFTOP
—
Reference voltage IF A/D converter
60
MONO_IN
I
Mono input
61,62
AVSS
—
Analog ground
63,64
NC
—
Not connected
65,66
AVSUP
—
Analog power supply 5V
67
ANA_IN1+
I
IF input 1
68
ANA_IN-
I
IF common(can be left vacant, only if IF input 1 is also not in use)
69
ANA_IN2+
I
IF input 2(can be left vacant, only if IF input 1 is also not in use)
70
TESTEN
I
Test pin
71
XTAL_IN
I
C
rystal oscillator
72
XTAL_OUT
O
73
TP
—
Test pin
74
AUD_CL_OUT
O
Audio clock output(18.432MHz)
75,76
NC
—
Not connected
77
D_CTR_I/O_1
I/O
D_CTR_I/O_1
78
D_CTR_I/O_0
I/O
D_CTR_I/O_0
79
ADR_SEL
I
I2C Bus address select
80
STANDBYQ
I
Stand-by(low-active)
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