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INTERRUPT[3:0]

A

b

I/O

External interrupts

C4

a. 5 V tolerant
b. T1, T2, T3 and T4.

OUTPLEFT

AC3

O

Left channel, differential positive current output

OUTMLEFT

AB1

O

Left channel, differential negative current output

OUTPRIGHT

AC4

O

Right channel, differential positive current output

OUTMRIGHT

AB4

O

Right channel, differential negative current output

ROUT

AF11

O

Red output

GOUT

AE11

O

Green output

BOUT

AD12

O

Blue output

COUT

AF9

O

Chroma output

CVOUT

AD10

O

Composite video output

YOUT

AE10

O

Luma output

NOT_HSYNC

A

AE20

I/O

Horizontal sync

C4

EVENNOTODD

a

AF20

I/O

Vertical sync

C4

a. 5 V tolerant

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Bit 0

SC0_DATAOUT or ASC0_TXD

a

Bit 1

SC0_DATAIN or ASC0_RXD

a

Bit 2

SC0_CG_EXTCLK

Bit 3

SC0CG_CLK or SMCDSS_CLK

b

Bit 4

(SCO_RESET)

Bit 5

(SC0_NOT_SETVCC)

Bit 6

SC0_DIR or ASC0_NOTOE

c

,

(SC0_NOT_SETVPP)

Bit 7

(SC0_DETECT)

a. ASC0 TX/RX data becomes smartcard TX/RX data when the ASC module is used in

smartcard mode.

b. Output function between PIO or smartcard module clock generator alternate function and

clock generator module frequency synthesizer clock is selected by bit 28 in the interconnect
register CONFIG_CONTROL_A (SMCARDA_DSSSMCLK_NOT_PIOBIT3). If the DSS
smartcard mode is selected (bit 28 = 1), this overrides the normal PIO or PIO alternate
function output.

c. When ASC0 is used in nonsmartcard mode, the smartcard direction signal becomes an active

low ASC TX output enable signal. The signals are in fact the same, that is, SC0_DIR = 0
means smartcard TX is active.

Bit 0

SC1_DATAOUT or ASC1_TXD

a

Bit 1

SC1_DATAIN or ASC1_RXD

a

Bit 2

SC1_CG_EXTCLK

Bit 3

SC1CG_CLK or SMCDSS_CLK

b

Bit 4

 (SC1_RESET)

Bit 5

YC[1]

YC[1], (SC1_NOT_SETVCC)

Bit 6

SC1_DIR or ASC1_NOTOE

c

,

(SC1_NOT_SETVPP)

Bit 7

YC[0] (SC1_DETECT)

YC[0]

a. ASC1 TX/RX data becomes smartcard TX/RX data when the ASC module is used in

smartcard mode.

b. Output function between PIO or smartcard module clock generator alternate function and

clock generator module frequency synthesizer clock is selected by bit 29 in the interconnect
register CONFIG_CONTROL_A (SMCARDB_DSSSMCLK_NOT_PIOBIT3). If the DSS
smartcard mode is selected (bit 29 = 1) this overrides the normal PIO or PIO alternate function
output.

c. When ASC1 is used in nonsmartcard mode the smartcard direction signal becomes an active

low ASC TX output enable signal. The signals are in fact the same, that is, SC1_DIR = 0
means smartcard TX is active.

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Bit 0

MAFE_HC1 or NOT_ASC4_RTS

a

Bit 1

MAFE_DOUT or ASC4_TXD

a

Bit 2

MAFE_DIN or ASC4_RXD

a

Bit 3

MAFE_FS or NOT_ASC4_CTS

a

Bit 4

MAFE_SCLK

Bit 5

PWM_CAPTURE0

Bit 6

PWM_COMPARE0

Bit 7

PWM_OUT0

a. Controlled by bit MAFE_OR_UART4_SEL in interconnect register CONFIG_CONTROL_D

(bit 20).

Bit 0

SSC0_MTSR_DIN or SSC0_MRST_DIN

SSC0_MTSR_DOUT or SSC0_MRST_DOUT

a

Bit 1

SSC0_SCLKIN

SSC0_SCLKOUT

Bit 2

SSC1_MTSR_DIN or SSC1_MRST_DIN

SSC1_MTSR_DOUT or SSC1_MRST_DOUT

b

Bit 3

SSC1_SCLK

SSC1_SCLK

Bit 4

NOT_CD_REQ[0] or PCMI_LRCLK

I1284PERILOGICHIGH

Bit 5

Slave mode I1284HOSTLOGICHIGH or
PCMI_DATA

Master mode I1284HOSTLOGICHIGH

Bit 6

NOT_CD_REQ[1] or PCMI_SCLK

I1284INNOTOUT

Bit 7

PWM_OUT1

a. Output function selected by bit 24 in interconnect configuration register

CONFIG_CONTROL_B (COMMS_SSC0_DOUT_MRST_NOTMTSR_MUXSEL)

b. Output function selected by bit 25 in interconnect configuration register

CONFIG_CONTROL_B (COMMS_SSC1_DOUT_MRST_NOTMTSR_MUXSEL)

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Bit 0

TTXTREQUEST or OSDENABLE

OSDENABLE

a

Bit 1

CFC

TXTDATAOUT

b

Bit 2

YC[7]

YC[7]

Bit 3

ASC2_RXD

Bit 4

ASC2_TXD

c

Bit 5

PWM_CAPTURE2 or YC[6]

YC[6]

Bit 6

SCCG_EXTCLK

PWM_COMPARE2

Bit 7

PWM_OUT2

a. OSDENABLE output function is selected rather than PIO by interconnect configuration

register CONFIG_CONTROL_C, bit 2 (CONFIG_OTHER_ALT_PIOPORT4[0]). The output
can then be turned off by the MPEG video decoder to use OSDENABLE as an input.

b. TXTDATAOUT function selected by interconnect configuration register

CONFIG_CONTROL_C, bit 3 (CONFIG_OTHER_ALT_PIOPORT4[1])

c. After reset, register CONFIG_CONTROL_C bit 4 must be set to 1 to pass PIO data or to use

ASC2_TXD in alternate output PIO mode.

Bit 0

IRB_IR_IN

a

Bit 1

IRB_UHF_IN

b

Bit 2

Infrared transmitter/receiver drive PPM

Bit 3

Infrared transmitter/receiver drive jack (0 or z)
open drain jack output

c, d

Bit 4

YC[5]

ASC3_TXD or YC[5]

e

Bit 5

ASC3_RXD or YC[4]

YC[4]

Bit 6

NOT_ASC3_CTS or YC[3]

YC[3]

Bit 7

YC[2]

NOT_ASC3RTS or YC[2]

e

a. The wake-up from low power mode function is enabled by interconnect configuration register

CONFIG_CONTROL_D, bit 21 (RC_IRDA_DATA_IN_EN).

b. The wake-up from low power mode function is enabled by interconnect configuration register

CONFIG_CONTROL_D, bit 22 (UHF_IN_EN).

c. PIO needs to be configured as open drain in alternate output mode to use infrared transmitter/

receiver drive jack.

d. After reset, bit 5 in CONFIG_CONTROL_C must be set to 1 to pass PIO data or use infrared

transmitter/receiver drive jack in alternate function mode.

e. Output function selected by bit 11 in CONFIG_CONTROL_E

(CONFIG_OTHER_ALT_PIO_YC)