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NOT_EMIRAS or
NOT_CI_IORD

a

J2

O

Row address strobe for SDRAM

C4

NOT_EMICAS or
NOT_CI_IOW

a

J1

O

Column address strobe for SDRAM

E8

NOT_EMICSA

K4

O

Peripheral chip select A

E8

NOT_EMICSB

K3

O

Peripheral chip select B

E8

NOT_EMICSC

K2

O

Peripheral chip select C

E8

NOT_EMICSD

K1

O

Peripheral chip select D

E8

NOT_EMICSE

L4

O

Peripheral chip select E

E8

NOT_EMICSF

L3

O

Peripheral chip select F

E8

NOT_EMIBE[1:0]

L1, L2

O

External device data bus byte enable. 1 bit per
byte of the data bus.

E8

NOT_EMIOE or
NOT_CI_OE

M1

O

External device output enable.

E8

NOT_EMILBA or
NOT_CI_WEA

N3

O

Flash device load burst address.

E8

EMIWAITNOTTREADY

b

N4

I

External memory device target ready indicator

C4

EMIRDNOTWR

N2

O

External read/write access indicator. Common to
all devices.

E8

EMIDATA[15:0]

c

I/O

External common data bus.

E8

EMIADDR[25:2]

d

e

O

External common address bus

E8

NOT_EMIREQGNT

J3

O

Bus request/grant indicator

E8

NOT_EMIACKREQ

b

H1

I

Bus grant/request indicator

C4

EMIBOOTMODE0

b

H3

I

External power-up port size indicator

C4

EMISDRAMCLK

A1

O

SDRAM clock

E8

EMIFLASHCLK

A2

O

Peripheral clock

E8

a. Or equivalent ATA HDD interface signal.
b. 5 V tolerant
c. B3, A3, A4, B4, C4, A5, B5, C5, A6, B6, C6, D6, A7, B7, C7 and A8.
d. EMIADDR[19:20] are used as ATA HDD interface function: ATA CS0 and CS1. There is no

interconnect configuration control register bit to select this function. The addresses are just
reused as chip selects.

e. B8, C8, A9, B9, C9, D9, A10, B10, C10, A11, B11, C11, A12, B12, C12, D12, A13, B13, C13,

D13, A14, B14, C14 and D14.

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TSIN2LBYTECLK

a

L24

I/O

Transport stream bit clock

C4

TSIN2LBYTECLKVALID

a

L26

I/O

Transport stream bit clock valid edge

C4

TSIN2LERROR

a

L25

I/O

Transport stream packet error

C4

TSIN2LPACKETCLK

a

J25

I/O

Transport stream packet strobe

C4

TSIN2LDATA[7:0]

a

b c

I/O

Transport stream data

C4

a. 5 V tolerant
b. H25, H24, H23, J26, J24, K26, K25 and K24
c. TSIN2LDATA7 is used for data input in serial mode.

TSIN1BYTECLK

a

P23

I

Transport stream bit/byte clock

C4

TSIN1BYTECLKVALID

a

P26

I

Transport stream bit/byte clock valid edge

C4

TSIN1ERROR

a

P25

I

Transport stream packet error

C4

TSIN1PACKETCLK

a

P24

I

Transport stream packet strobe

C4

TSIN1DATA[7:0]

a

b

,

c

I

Transport stream data in

C4

a. 5 V tolerant
b. M26, M25, M24, M23, N26, N25, N24 and N23.
c. TSIN1DATA7 is used for data input in serial mode.

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PIO0[0:7]

A

b

I/O

Parallel input/output pin or alternative function

P4

PIO1[0:7]

a

c

I/O

P4

PIO2[0:7]

a

d

I/O

P4

PIO3[0:7]

a

e

I/O

P4

PIO4[0:7]

a

f

I/O

P4

PIO5[0:7]

a

g

I/O

P4

a. 5 V tolerant
b. U2, U1, U3, V4, V3, V2, V1 and W4
c. W3, W2, W1, Y3, Y2, Y1, AA4 and AE1
d. AF1, AD2, AE2, AF2, AF3, AD3, AE3 and AD4
e. AE5, AE4, AF5, AF4, AD6, AD15, AD5 and AE15
f. AF15, AD16, AE16, AF16, AC17, AD17, AF18 and AE17
g. AF17, AD18, AE18, AC19, AD19, AE19, AF19 and AD20

SCLK

B

AD13

O

Serial clock

C4

PCMDATA[1]

b

AE14

O

PCM data out

C4

PCMCLK

b

AE13

I/O

External PCM clock input or internal PCM clock
output

C4

LRCLK

b

AF13

O

Left/right clock

C4

SPDIF

b

AC15

O

Digital audio output

C4

a. Note: Digital audio input pins PCMI_SCLK, PCMI_DATA and PCMI_LRCLK are alternate

functions for NOT_CD_REQ[1], I1284HOSTLOGICHIGH, and NOT_CD_REQ[0], on PIO port
3 bits [6:4]

b. 5 V tolerant

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SMIADDR[13:0]

a

O

Audio/video core SDRAM address bus

S8

SMIDATA[15:0]

b

I/O

Audio/video core SDRAM data bus

S8

NOT_SMICS0

V25

O

Audio/video core SDRAM chip select for 1st
SDRAM

S8

NOT_SMICS1

V26

O

Audio/video core SDRAM chip select for 2nd
16 Mbit SDRAM

S8

NOT_SMICAS

U23

O

Audio/video core SDRAM column address strobe

S8

NOT_SMIRAS

U24

O

Audio/video core SDRAM row address strobe

S8

NOT_SMIWE

U25

O

Audio/video core SDRAM write enable

S8

SMIMEMCLKIN

T23

I

Audio/video core SDRAM memory clock input

S8b

SMIMEMCLKOUT

U26

O

Audio/video core SDRAM memory clock output

S8

SMIDATAML

T24

O

Audio/video core SDRAM data bus lower byte
enable

S8

SMIDATAMU

T25

O

Audio/video core SDRAM data bus upper byte
enable

S8

a. AC24, AC23, AD26, AD25, AD24, AD23, AE26, AE25, AE24, AE23, AF26, AF25, AF24 and

AF23.

b. V24, W26, W25, W24, W23, Y26, Y25, Y24, AA26, AA25, AA24, AB26, AB25, AB24, AC26

and AC25.

P1284DATA[7:0]

A

b

I/O

1284 data or 1394 AV data

I14

NOT_P1284SELECTIN

a

E24

I/O

1284 or 1394 AV control signals

I14

NOT_P1284INIT

a

E25

I/O

I14

NOT_P1284FAULT

a

E26

I/O

I14

NOT_P1284AUTOFD

a

D24

I/O

I14

P1284SELECT

a

D25

I/O

I14

P1284PERROR

a

D26

I/O

I14

P1284BUSY

a

C25

I/O

I14

NOT_P1284ACK

a

C26

I/O

I14

NOT_P1284STROBE

a

B26

I/O

I14

a. 5 V tolerant
b. F26, F25, F24, F23, G26, G25, G24 and H26.