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The TSH343 is a triple single-supply video buffer featuring an internal gain of 6dB and a 
large bandwidth of 280MHz. The main advantage of this circuit is that its input DC level 
shifter  allows  for  video  signals  on  75Ω  video  lines  without  damage  to  the 
synchronization  tip  of  the  video  signal,  while  using  a  single  5V  power  supply  with  no 
input capacitor. The DC level shifter is internally fixed and optimized to keep the output 
video  signals  between  low  and  high  output  rails  in  the  best  position  for  the  greatest 
linearity. Chapter 4 of this datasheet gives technical support when using the TSH343 as 
Y-Pb-Pr driver for video DAC output on a video line (see TSH344 for RGB signals). The 
TSH343 is available in the compact SO8 plastic package for optimum space-saving.

 Bandwidth: 280MHz

 5V single-supply operation

 Internal input DC level shifter

 No input capacitor required

 Internal gain of 6dB for a matching between 3 channels

 AC or DC output-coupled

 Very low harmonic distortion

 Slew rate: 780V/μs

 Specified for 150Ω and 100Ω loads

 Tested on 5V power supply

 Data min. and max. are tested during production

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 
67,108,864  bits.  It is  internally  configured  as  a  quad-bank  DRAM  with  a synchronous 
interface (all signals are registered on the positive edge of the clock signal, CLK). Each 
of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. 
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns 
by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at 
a  selected  location  and  continue for  a  programmed  number  of  locations  in  a
programmed sequence. Accesses begin with the registration of an ACTIVE command, 
which  is  then ollowed  by  a  READ  or  WRITE  command.  The  address bits  registered 
coincident  with  the  ACTIVE  command are  used  to  select  the  bank  and  row  to  be 
accessed (BA0, BA1 select the bank; A0-A11 select the row). 

 PC66-, PC100- and PC133-compliant

 143 MHz, graphical 4 Meg x 16 option

 Fully synchronous; all signals registered on positive edge of system clock

 Internal pipelined operation; column address can be changed every clock cycle

 Internal banks for hiding row access/precharge

 Programmable burst lengths: 1, 2, 4, 8 or full page

 Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and AutO 

Refresh Modes

 Self Refresh Modes: standard and low power

 64ms, 4,096-cycle refresh

 LVTTL-compatible inputs and outputs

 Single +3.3V ±0.3V power supply