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 Input Data Format

 1-byte Command code

 Block Lock protection

 The  BP0~BP1  status  bit  defines  the  size  of  the  area  to  be  software  protected 

against Program and Erase instructions.

 Auto Erase and Auto Program Algorithm

 Automatically erases and verifies data at selected sector

 Automatically programs and verifies data at selected page by an internal algorithm 

that automatically times the program pulse widths (Any page to be programed 
should have page in the erased state first)

 Status Register Feature

 Electronic Identification

 JEDEC 2-byte Device ID

 RES command, 1-byte Device ID

HARDWARE FEATURES
 SCLK Input

 Serial clock input

 SI Input

 Serial Data Input

 SO Output

 Serial Data Output

 WP# pin

 Hardware write protection

 HOLD# pin pause the chip without diselecting the chip

 PACKAGE

 8-pin SOP (150mil)

 All Pb-free devices are RoHS Compliant

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA 
of  load  current.  It  has  the  same  pin-out  as  National  Semiconductor’s  industry  standard 
LM317.  The  LM1117  is  available  in  an  adjustable  version,  which  can  set  the  output 
voltage  from  1.25V  to  13.8V  with  only  two  external  resistors.  In  addition,  it  is  also 
available  in  five  fixed  voltages,  1.8V,  2.5V,  2.85V,  3.3V,  and  5V.  The  LM1117  offers 
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference  to  as-sure  output  voltage  accuracy  to  within  ±1%.  The  LM1117  series  is 
available  in  SOT-  223,  TO-220,  and  TO-252  D-PAK  packages.  A  minimum  of  10μF 
tantalum  capacitor  is  required  at  the  output  to  improve  the  transient  response  and 
stability.

 Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

 Space Saving SOT-223 Package

 Current Limiting and Thermal Protection

 Output Current 800mA

 Line Regulation 0.2% (Max)

 Load Regulation 0.4% (Max)

 Temperature Range

 LM1117 0°C to 125°C

 LM1117I -40°C to 125°C

 2.85V Model for SCSI-2 Active Termination

 Post Regulator for Switching DC/DC Converter

 High Efficiency Linear Regulators 15

 32” TFT TV Service Manual 10/01/2005

 Battery Charger

 Battery Powered Instrumentation

         

The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with  the  HEF4053B.  It  is  specified  in  compliance  with  JEDEC  standard  no.  7A. The 
74HC4053;  74HCT4053  is  triple  2-channel  analog  multiplexer/demultiplexer  with  a
common  enable  input  (E).  Each  multiplexer/demultiplexer  has  two  independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs 
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to 
S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to 
S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and 
E). The VCC  to GND  ranges  are  2.0  V  to 10.0  V  for  74HC4053 and  4.5 V  to  5.5 V  for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).

 Low ON resistance:

 80 W (typical) at VCC - VEE = 4.5 V

 70 W (typical) at VCC - VEE = 6.0 V

 60 W (typical) at VCC - VEE = 9.0 V

 Logic level translation:

 To enable 5 V logic to communicate with ±5 V analog signals

 Typical ‘break before make’ built in

 Complies with JEDEC standard no. 7A

 ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-

A115-A exceeds 200 V

 Multiple package options

 Specified from -40 °C to +85 °C and from -40 °C to +125 °C

 Analog multiplexing and demultiplexing

 Digital multiplexing and demultiplexing

 Signal gating