Sharp LC-32CT2E (serv.man2) Service Manual ▷ View online
9 WINBOND W9425G6EH DDR SDRAM 128M
9.1
General Description
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access
memory (DDR SDRAM), organized as 4,194,304 words u 4 banks u 16 bits. W9425G6EH
delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the
personal computer industrial standard, W9425G6EH is sorted into the following speed
grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 and CL4
specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade
which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the
DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
memory (DDR SDRAM), organized as 4,194,304 words u 4 banks u 16 bits. W9425G6EH
delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the
personal computer industrial standard, W9425G6EH is sorted into the following speed
grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 and CL4
specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade
which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the
DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing
reference point for the differential clock is when the CLK and CLK signals cross during a
transition. Write and Read data are synchronized with the both edges of DQS (Data
Strobe). By having a programmable Mode Register, the system can change burst length,
latency cycle, interleave or sequential burst to maximize its performance.
reference point for the differential clock is when the CLK and CLK signals cross during a
transition. Write and Read data are synchronized with the both edges of DQS (Data
Strobe). By having a programmable Mode Register, the system can change burst length,
latency cycle, interleave or sequential burst to maximize its performance.
9.2
Features
- 2.5V r0.2V Power Supply for DDR333/400
- 2.6V r0.1V Power Supply for DDR500
- Up to 250 MHz Clock Frequency
- Double Data Rate architecture; two data transfers per clock cycle
- Differential clock inputs (CLK and CLK )
- DQS is edge-aligned with data for Read; center-aligned with data for Write
- CAS Latency: 2, 2.5, 3 and 4
- Burst Length: 2, 4 and 8
- Auto Refresh and Self Refresh
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = 1
- 7.8µS refresh interval (8K/64 mS refresh)
- Maximum burst refresh cycle: 8
- Interface: SSTL_2
- 2.6V r0.1V Power Supply for DDR500
- Up to 250 MHz Clock Frequency
- Double Data Rate architecture; two data transfers per clock cycle
- Differential clock inputs (CLK and CLK )
- DQS is edge-aligned with data for Read; center-aligned with data for Write
- CAS Latency: 2, 2.5, 3 and 4
- Burst Length: 2, 4 and 8
- Auto Refresh and Self Refresh
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = 1
- 7.8µS refresh interval (8K/64 mS refresh)
- Maximum burst refresh cycle: 8
- Interface: SSTL_2
9.3
Absolute Maximum Ratings
9.4
Pinning
10 ELPIDA EDE5116AJBG DDR SDRAM
10.1 General Description
There are 2 Elpida EDE5116AJBG (32M x 16 bits) DDR2 SDRAM used for NEC
EMMA3SL microcontroller functions and MPEG2/MPEG4 decoding functions. Data pins
are connected parallel and the address selection is varied for different memory access
locations.
EMMA3SL microcontroller functions and MPEG2/MPEG4 decoding functions. Data pins
are connected parallel and the address selection is varied for different memory access
locations.
10.2 Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data
for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both
edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus
efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4
organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data
for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both
edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus
efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4
organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation
11.3 Absolute Maximum Ratings
Click on the first or last page to see other LC-32CT2E (serv.man2) service manuals if exist.