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The    MST6WB7GQ-3    is    a    high    performance    and    fully    integrated    IC    for    multi-
function  LCD  monitor/TV  with resolutions  up  to  full  HD  (1920x1080). It  is configured  
with    an   integrated    triple-ADC/PLL,    an    integrated DVI/HDCP/HDMI  receiver,  a  multi-
standard TV video and audio decoder, two video de-interlacers, two scaling engines, the 
MStarACE-3  color  engine,  an  on-screen  display  controller,  an  8-bit  MCU  and  a  built-in 
output  panel interface.        By  use  of  external  frame  buffer,  PIP/POP  is  provided  for 
multimedia applications.    Furthermore, 3-D video decoding and processing are fulfilled 
for  high-quality  TV  applications.  To  further  reduce  system  costs, the    MST6WB7GQ-3  
also    integrates    intelligent    power    management    control    capability    for    green-mode
requirements and spread-spectrum support for EMI management.

 Input supports up to UXGA & 1080P

 Panel supports up to full HD (1920x1080)

 TV decoder with 3-D comb filter

 Multi-standard TV sound demodulator and decoder

 10-bit triple-ADC for TV and RGB/YPbPr

 10-bit video data processing

 Integrated DVI/HDCP/HDMI compliant receiver

 High-quality dual scaling engines & dual 3-D video de-interlacers

 3-D video noise reduction

 Full function PIP/PBP/POP

 MStarACE-3 picture/color processing engine

 Embedded On-Screen Display (OSD) controler engine

 Built-in MCU supports PWM & GPIO

 Built-in dual-link 8/10-bit LVDS transmitter

 5-volt tolerant inputs

 Low EMI and power saving features

 296-pin LQFP

 Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM

 Automatic TV standard detection

 Motion adaptive 3-D comb filter for NTSC/PAL

 8 configurable CVBS & Y/C S-video inputs

 Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip

 Macrovision detection

 CVBS video output

 Digital low IF architecture

 Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution

 Maximum IF analog gain of 37dB in addition to digital gain

 Programmable TOP to accommodate different tuner gain to optimize noise and 

linearity performance

 Supports BTSC/NICAM/A2/EIA-J demodulation and decoding

 FM stereo & SAP demodulation

 L/Rx4, mono, and SIF audio inputs

 L/Rx3 loudspeaker and line outputs

 Supports sub-woofer output

 Built-in audio output DAC’s

 Audio processing for loudspeaker channel, including volume, balance, mute, tone, 

EQ, and virtual stereo/surround

 Optional advanced surround available (Dolby1, SRS2, BBE3… etc) 

 I2S digital audio input & output

 S/PDIF digital audio input & output

 HDMI audio channel processing capability

 Programmable delay for audio/video synchronization

 Three analog ports support up to UXGA

 Supports HDTV RGB/YPbPr/YCbCr

 Supports Composite Sync and SOG (Sync-on-Green) separator

 Automatic color calibration

 Two HDMI input ports with built-in switch   

 Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color 

resolution   

 Single link on-chip DVI 1.0 compliant receiver

 High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver

The  MC-10085/86/87/88  devices,  EMMA3SL/HD,  are  part  of  the  third  generation  of 
multimedia processors based on NEC’s Enhanced MultiMedia Architecture (EMMA™). This 
device  provides  nearly  all  the  functionality  required  to  realise  a  high  performance  and  cost-
effective integrated digital TV.

NEC EMMA3SL integrates the functions of a TS de-multiplexer, a DMA controller, MPEG2, 
H.264 (MPEG-4 part 10) and VC-1 video decoders, an audio processor, graphics and display 
engines, a video encoder and DAC, and various interfaces to support peripheral modules. 

The  device  has  been  designed  with  a  memory  interface  using  glueless  logic  which  supports 
DDR2  SDRAM.  The  MC-10085/86/87/88  incorporate  a  processor,  two  main  buses  and  a 
peripherals bus. The processor is a MIPS32 24KEc core and can access all modules within the 
device.

Figure 6.1 Block Diagram of NEC EMMA3SL

Main Processor
- High Performance MIPS32 24KEc CPU core
- 32 bit RISC MIPS architecture
- Supports the MIPS16, MIPS-I, MIPS-II and MIPS-III instruction sets
- 16 KByte instruction cache, 16 KByte data cache
- 2 way cache accessing
- EJTAG debug support

Unified Memory Interface
- Supports 16/32 bit bus width DDR2-SDRAM
- Unified CPU/MPEG/Graphics memory
- Supports data rates up to 655 MHz
- Supports 256 ~ 2048 Mbit total memory

ROM/GIO Interface
- Total address area 64Mbyte for ROM
- Supports normal, page and flash ROM
- Supports NOR and NAND flash ROM
- 4 chip select signals for both ROM and GIO
- 16 MByte total address area for GIO
- Up to 4 Gbit NAND
- PCMCIA support

Stream Processor
- Supports MPEG2-TS (DVB)
- Four dedicated transport stream input ports – two serial and two parallel
- One further channel for input of transport streams via a CPU-controlled register
- Total maximum input bit rate of 108 Mbits/sec
- 36 PID filters

• 1 Video PIDs
• 2 Audio PIDs
• 1 PCR PIDs
• 32 general PIDs

- 32 section filters (8-Byte/16-Byte depth) in four configurable banks
- High Speed Data output port for interfacing to external devices
- DVB descrambling support

Descrambler
- Supports DES, 3DES and AES

DMA
- Supports DMA transfer between internal units and DDR2-SDRAM