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VHiCXA2069Q-1 (ASSY:FIC1301)

S2-compatible 7-input, 3-output AV switch

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Block diagram

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63

TV

I

Video signal input

1

V1

I

Composite video signal input

8

V2

I

15

V3

I

22

V4

I

30

V4

I

60

V4

I

3

Y1

I

Y/C separation signal input, used for luminance signal input

10

Y2

I

YIN1: Input for signal created by Y/C separation of VOUT1 output

17

Y3

I

24

Y4

I

49

YIN1

I

5

C1

I

Y/C separation signal input, used for chrominance signal input

12

C2

I

CIN1: Input for signal created by Y/C separation of VOUT1 output

19

C3

I

26

C4

I

51

CIN1

I

62, 2

LTV, LV1

I

Audio signal input

9, 16

LV2, LV3

I

23, 29

LV4, LV5

I

59, 64

LV6, RTV

I

4, 11

RV1, RV2

I

18, 25

RV3, RV4

I

31, 61

RV5, RV6

I

53

VOUT1

O

Video signal output, used for composite vide signal output

41

VOUT3

O

44

V/YOUT2

O

Video signal output, controlled via 12C bus and used for composite video signal output

56

YOUT1

O

Power or luminance signal output is selected.

39

YOUT3

O

Video signal output, used for luminance signal output

58

COUT1

O

Video signal output, used for chrominance signal output

47

COUT2

O

37

COUT3

O

52

LOUT1

O

Audis signal output

43

LOUT2

O

38

LOUT3

O

54

ROUT1

O

45

ROUT2

O

40

ROUT3

O

6

S2-1

I

Used for detection of S2-compatible DC that is superimposed to C signal.

13

S2-2

I

4:3 image signal is selected when voltage ? 1.3V, 4:3 letterbox signal when 1.3V

20

S2-3

I

< voltage ? 2.5V, and 16:9 squeeze signal when voltage > 2.5V. 4:3 image signal is

27

S2-4

I

 selected when the pins are open because they are pulled down to GND via 100K?.

7

S-1

I

Used for selection between composite video signal and S signal.

14

S-2

I

Detection result is written to the status register. S signal is selected when voltage ?

21

S-3

I

3.5V, and composite video signal when voltage > 3.5V. Composite video signal is

28

S-4

I

selected when the pins are open because they are pulled down to 5V via 100K?.

32

ADR

I

Used for selection of slave address for 12C bus.
90H is selected when voltage ? 1.5V, and 92H when ? 2.5V.
90H is selected when the pin are open.

33

SCL

I

12C bus signal input

34

SDA

I

12C bus signal input

36

DC OUT

O

Used for output of S2-compatible DC that is superimposed to COUT3.
DC superimposition is done by connecting to COUT3 via capacitor. The pin is
controlled via 12C bus.
Connection of 4.7k? external resistor provides output impedance of 10?3K? that
conforms to S2.

55

TRAP1

I

Connected to trap circuit for sub carrier.

46

TRAP2

I

48

MUTE

I

Mute for audio signal output.
Mute is on when voltage ? 1.3V and off when voltage ? 2.5V.
Mute is off when the pin is open.

50

BIAS

I

Internal reference bias input.
Connected to GND via capacitor.

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VHiMM1519XQ-1 (IC1401)

Component Input Video Switch

»

Block diagram

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1

VIDEO 1-L1

I

D-pin connection line input

2

VIDEO 1-L2

I

3

VIDEO 1-L3

I

11

VIDEO 2-L1

I

12

VIDEO 2-L2

I

13

VIDEO 2-L3

I

21

VIDEO 3-L1

I

22

VIDEO 3-L2

I

23

VIDEO 3-L3

I

4, 14, 39,45, 52, 58

VCC

––

Analog power supply (9V)

51

AVCC

––

5

VIDEO 2-Y

I

Y signal input

15

VIDEO 3-Y

I

53

TUNER-Y

I

59

VIDEO 1-Y

I

24

DGND

––

6, 8, 16, 18, 33,35,

GND

––

37, 41, 43, 47, 49,

54, 58, 60, 62

7

VIDEO 2-Pb

I

Chrominance input

9

VIDEO 2-Pr

I

17

VIDEO 3-Pb

I

19

VIDEO 3-Pr

I

55

TUNER-Pb

I

57

TUNER-Pr

I

61

VIDEO 1-Pb

I

63

VIDEO 1-Pr

I

10

VIDEO 2-SW

I

D-pin connection check switch line input

20

VIDEO 3-SW

I

32

MONO-SW

I

64

VIDEO 1-SW

I

25

ADDRESS

I

Slave address input

26

SDA

I/O

12C bus data input/output

27

SCL

I

12C bus clock input

28

DVCC

––

Digital power supply (5V)

29

L3 OUT

O

Monitor output line output

30

L2 OUT

O

31

L1 OUT

O

34

Pr OUT 3

O

Image output

36

Pb OUT 3

O

38

Y OUT 3

O

40

Pr OUT 2

O

42

Pb OUT 2

O

44

Y OUT 2

O

46

Pr OUT 1

O

48

Pb OUT 1

O

50

Y OUT 1

O