Sharp LC-30HV4E (serv.man2) Service Manual ▷ View online
46
LC-30HV4E
Pin No.
Pin Name
Type
Description
1
NC
––
Non-connection
2
SP_CP2
I
Input of clamp signal from synchronous separation IC (for 15K system)
3
SP_VD
I
Input of vertical synchronization signal from synchronous separation IC
4
GND
––
Ground
5
SP_HD
I
Input of horizontal synchronization signal from synchronous separation IC
6
VD3
O
Output of vertical synchronization signal to synchronous separation IC
7
HD3
O
Output of horizontal synchronization signal to synchronous separation IC
8
SP_CP1
I
Input of clamp signal from synchronous separation IC (normal)
9
TDI
I
SP data input
10
TMS
I
SP mode input
11
TCK
I
SP clock input
12
TEXT_HD
O
TEXT_HD output
13
US_HD
I
RCA/TEXT horizontal synchronization signal input
14
TEXT_VD
O
TEXT_VD output
15
Vcc3.3V
––
TEXT_VD output
16
US_VD
I
RCA/TEXT vertical synchronization signal input
17
GND
––
Ground
18
MODEA
I
Mode selection signal A
19
MODEB
I
Mode selection signal B
20
MODEC
I
Mode selection signal C
21
SELA
I
Input of HD switching control signal for main video chroma/RCA
22
SELO
I
Input of control signal for TEXT synchronization signal output
23
SELC
I
Input of control signal for TEXT synchronization signal output
24
TDO
O
ISP data output
25
GND
––
Ground
26
Vcc3.3V
––
Power supply
27
VD1
I
Input of vertical synchronization signal from main video chroma IC
28
HD1
I
Input of horizontal synchronization signal from main video chroma IC
29
PL_VD
O
Vertical synchronization signal output
30
PL_HD
O
Horizontal synchronization signal output
31
PL_CP
O
Clamp signal output
32
PL_BLK
O
H blank signal output
33
MODED
I
Mode selection signal D
34
NC
––
Mode selection signal D
35
Vcc3.3V
––
Power supply
36
NC
––
Non-connection
37
CC_HD
O
Horizontal synchronization signal for closed caption
38
ow_vblk
I
Auto wide V blank signal input
39
HDS
O
Output of horizontal synchronization signal for PC board
40
VDS
O
Output of vertical synchronization signal for PC board
41
HD2
I
Input of horizontal synchronization signal from sub video chroma IC
42
VD2
I
Input of vertical synchronization signal from sub video chroma IC
43
clk
I
Clock input
44
NC
––
Non-connection
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Pin mapping
47
LC-30HV4E
Pin No.
Pin Name
Type
Description
1
BIAS
––
ADC bias
2
VRT
––
ADC upper limit bias
3
VDD1
––
ADC and DAC power supply (analog system)
4
TESTI1
I
Input for testing
5
VSS2
––
ADC GND (analog system)
6
VRB
––
Video signal input
7
YCIN
I
ADC lower limit bias
8
TEST
O
Reset control and test control before shipping
9
KILLER
I
Y/C separation and vertical enhancer OFF
10
TESTI2
I
Input for testing
11
VDD3
––
Power supply to logic (digital system)
12
VSS3
––
Logic and DRAM GND (digital system)
13
VDD2
––
DRAM power supply (digital system)
14
TESTI3
I
Input for testing
15
SCL
I
IIC BUS clock input
16
SDA
I
IIC BUS data input
17
MODE1
O
MODE1 output
18
TESTOUT
I
Input for testing
19
FSC
I
Clock input
20
VDD4
––
PLL power supply (analog system)
21
VSS4
––
PLL GND (analog system)
22
FIL
I
VCO control
23
PD
O
PLL detection output
24
VB2
––
DAC bias 2
25
YOUT
O
Luminance signal output
26
VSS1
––
DAC GND (analog system)
27
COUT
O
DAC GND (analog system)
28
VB1
––
DAC bias 1
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Pin mapping
48
LC-30HV4E
Pin No.
Pin Name
Type
Description
34, 36-44,
D[15:0]
I/O
Data bus D [15:0]
46, 48-52
23-26, 28, 30-32
D[23:16/PTA[7:0]
I/O
Data bus D [23:16] / I/O port A [7:0]
13-18, 20, 22
D[31:24/PTB[7:0]
I/O
Data bus D [31:24] / I/O port B [7:0]
86, 84, 82, 78-72,
A[25:0]
O
Address bus A [15:0]
70-68-60, 56-53
96
CS0
O
Chip select 0/
98
CS2/PTK[0]
O/(I/O)
Chip select 2 / I/O port K [0]
99
CS3/PTK[1]
O/(I/O)
Chip select 3 / I/O port K [1]
100
CS4/PTK[2]
O/(I/O)
Chip select 4 / I/O port K [2]
101
CS5/CE1E/PTK[3]
O/(I/O)
Chip select 5 / CE1 (area 5SPCMIA)/O port K [3]
102
CS6/CE1B
O
Chip select 6 / CE1 (area 6SPCMIA)
87
BS/PTK[4]
O/(I/O)
Bus cycle start signal / I/O port K [4]
118
RAS3U/PTE[2]
O/(I/O)
RAS (area 3DRAM, SDRAM upper 32MB address) / I/O port E [2]
106
RAS3L/PTJ[0]
O/(I/O)
RAS (area 3DRAM, SDRAM upper 32MB address) / I/O port J [0]
119
RAS2U/PTE[1]
O/(I/O)
RAS (area 2DRAM, SDRAM upper 32MB address) / I/O port E [1]
107
RAS2L/PTJ[1]
O/(I/O)
RAS (area 2DRAM, SDRAM upper 32MB address) / I/O port JE [1]
108
CASLL/CAS/PTJ[2]
O/(I/O)
D7-D0 CAS (DRAM)/CAS (SDRAM) / I/O port J [2]
110
CASLH/PTJ[3]
O/(I/O)
D15-D18 CAS (DRAM) / I/O port J [3]
112
CASHL/PTJ[4]
O/(I/O)
D23-D16 CAS (DRAM) / I/O port J [4]
113
CASHH/PTJ[5]
O/(I/O)
D31-D24 CAS (DRAM) / I/O port J [5]
116
CAS2L/PTE[6]
O/(I/O)
D31-D24 CAS (DRAM) / I/O port J [5]
117
CAS2H/PTE[3]
O/(I/O)
D31-D24 CAS (DRAM) / I/O port J [5]
89
WE0/DQMLL
O
D7-D0 selection signal/DQM (SDRAM)
90
WE1/DQMLU/WE
O
D7-D0 selection signal/DQM (SDRAM)
91
WE2/DQMUL/
O/(I/O)
D23-D16 selection signal/DQM (SDRAM)/PCMCIA I/O port K [6]
ICIORD/PTK[6]
92
WE3/DQMUU/
O/(I/O)
D31-D24 selection signal/DQM (SDRAM)/PCMCIA I/O write I/O port K [7]
ICIOWR/PTK[7]
93
RD/WR
O
Read/Write switch signal
88
RD
O
Read strobe
105
CKE/PTK[5]
O/(I/O)
CK enable (for SDRAM only) / I/O port K [5]
123
WAIT
I
Hardware wait request
11-8
IRL[3:0]/IRQ[3:0]/
I
Hardware wait request
PTH[3:0]
12
IRQ4/PTH[4]
I
External interrupt request / I/O port H [4]
7
NMI
I
Non-maskable interrupt request
160
IRQOUT
O
Interrupt request output
182
WAKEUP/PTD[3]
O/(I/O)
Standby mode interrupt request output / I/O ports D [3]
159
TCLK/PTH[7]
I/O
TMU/RTC clock I/O / I/O port H [7]
191
DREQ0/PTD[4]
I
DMA request 0 / I/O port D [4]
114
DACK0/PTD[5]
O/(I/O)
DMA ACK 0 / I/O port D [5]
192
DREQ1/PTD[6]
I
DMA request 0 / I/O port D [6]
115
DACK1/PTD[7]
O/(I/O)
DMA ACK 1 / I/O port D [7]
189
DRAK0/PTD[1]
O/(I/O)
DMA ACK 1 / I/O port D [7]
190
DRAK1/PTD[0]
O/(I/O)
DMA ACK 0 / I/O port D [0]
171
RxD0/SCPT[0]
I
Receive data 0/SCI input port [0]
164
TxD0/SCPT[0]
O
Send data 0/SCI output port [0]
165
SCK0/SCPT[1]
I/O
Serial clock 0/SCI I/O port [1]
172
RxD1/SCPT[2]
I
Receive data 0/SCI input port [2]
166
TxD1/SCPT[2]
O
Send data 0/SCI output port [2]
167
SCK1/SCPT[1]
I/O
Serial clock 1/SCI I/O port [3]
174
RxD2/SCPT[4]
I
Receive data 0/SCI input port [4]
168
TxD2/SCPT[4]
O
Send data 2/SCI output port [4]
169
SCK2/SCPT[5]
I/O
Serial clock 2/SCI I/O port [5]
170
RTS2/SCPT[6]
O/(I/O)
Send request 2/SCI I/O port [6]
176
CTS2/IRQ5/SCPT[7]
I
Send clear 2/enternal interrupt request/SCI input port [7]
104
CE2B/PTE[5]
O/(I/O)
PC card 0 chip enable 2 / I/O port E [5]
126
IOIS16/PTG[7]
I
Write protect/input port G [7]
103
CE2A/PTE[[4]
O/(I/O)
PC card 1 chip enable 2 / I/O port E [4]
146, 149
CAP[1:2]
––
PLL external capacitor pin [1:2]
156
EXTAL
I
External clock/crystal oscillator input
155
XTAL
O
Crystal oscillator output
162
CKIO
I/O
System clock I/O
5
EXTAL2
I
RTC crystal oscillator input
4
XTAL
O
RTC crystal oscillator output
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Pin mapping
49
LC-30HV4E
Pin No.
Pin Name
Type
Description
»
Pin mapping
193
RESETP
I
Power-on reset request
124
RESETM
I
Manual reset request
122
BREQ
I
Bus request
121
BACK
O
Bus ACK
2, 1, 144
MD[2:0]
I
Clock mode select
196, 195
MD[4:3]
I
Area 0 bus width select
197
MD5
I
Endian select
194
CA
O
Chip active
158, 157
STATUS[1:0]/
I/O
Processor status [1:0] / I/O port J [7:6]
PTJ[7:6]
204-199
AN[5:0]/PTL[6:7]
I
A/D converter input [5:0]/input port L [5:0]
206, 207
AN[6:7]/DA[1:0]/
I/O
A/D converter input [6:7] / D/A converter output [1:0] / input port L [6:7]
PTL[6:7]
177-180, 185-188
PTC[7:0]/PINT[7:0]
I/O
I/O port C [7:0]/port interrupt [7:0]
184
PTD[2]/RESETOUT
I/O
I/O port D [2]/reset output
120, 94
PTE[0]/PTE[7]
I/O
I/O port E [0]/I/O port E [7]
136-143
PTF[7:0]/PINT[15:8]
I
I/O port E [7:0]/port interrupt [15:8]
127-131, 135
PTG[6:0]
I
I/O port G [6:0]
125
PTH[5]/ADTRG
I
I/O port H [5]/analog trigger
151
PTH[6]
I
I/O port H [6]
21, 29, 35, 47, 59,
Vcc
––
Power supply (3.3V)
71, 81, 85, 97,
111, 134, 154,
111, 134, 154,
163, 175, 183
145, 150
Vcc(PLL)
––
Power supply (3.3V)
3
Vcc(RTC)
––
Power supply (3.3V)
205
Avcc
––
Analog power supply (3.3V)
19, 27, 33, 45,
Vss
––
Power supply (0V)
57, 69, 79, 83, 95,
109, 132, 152,
153, 161, 173, 181
147, 148
Vss(PLL)
––
Power supply (0V)
6
Vss(TRC)
––
Power supply (0V)
198, 208
Avss
––
Analog power supply (0V)
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