DOWNLOAD Sharp LC-20B6E (serv.man10) Service Manual ↓ Size: 418.91 KB | Pages: 26 in PDF or view online for FREE

Model
LC-20B6E (serv.man10)
Pages
26
Size
418.91 KB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major ICs Information
File
lc-20b6e-sm10.pdf
Date
PREV: Sharp LC-20B6E (serv.man9) Service Manual

Sharp LC-20B6E (serv.man10) Service Manual ▷ View online

48
LC-20B6E
5. TU2201 RTUNQA016WJZZ
5.1. Block Diagram
PLL
Mix-Osc
IF-amp
AGC
Detector
SDA
SCL
Vcc
AS
33V
AGC
Pre-
filtering
Tracking
filters
Tracking
filters
Gain
controllable
pre-amplifiers
TV IF o/p
FM IF o/p
(10.7 MHz)
TV
FM
RF i/p
(TV)
RF i/p *
(FM)
RF i/p*
(FM)
* mutually exclusive
ADC
1
2
3
4
5
7
8
9
10
11
SYMBOL
PIN
DESCRIPTION
AGC
1
Gain Control Voltage
TU/FM
2
Tuning voltage monitor output / FM antenna input for R/ version
AS
3
I 
2
C-Bus Address Select
SCL
4
I 
2
C-Bus Serial Clock
SDA
5
I 
2
C-Bus Serial Data
n.c.
6
Not Connected
5V
7
Supply Voltage +5V
ADC
8
ADC Input 
(5)
V
T
9
Fixed tuning Supply Voltage +33V
FM-IF
10
10.7 MHz FM IF output
IF
11
Asymmetrical TV IF Output
GND
M1,M2,M3,M4 Mounting Tags (Ground)
NOTE
(5)  
Standard 5 level Analog to Digital Converter
5.2. Pinning
49
LC-20B6E
6. IC1602  VHITEA5114A-1
6.1. Pin Connections
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INPUT
GND
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
R OUTPUT
INPUT
FB OUTPUT
B OUTPUT
G OUTPUT
INPUT
INPUT
R
1
R
2
G
1
G
2
B
1
FB
1
FB
R
B
2
FB
2
FB
B
+
FB
G
V
CC
6.2. Block Diagrams
9
15
16
G = 2
14
G = 2
G = 2
1
2
3
10
11
12
13
4
5
6
7
8
OR
V
REF
TEA5114A
50
LC-20B6E
7. IC2203  VHIDRX3960A-1
7.1. Block Diagram
Clock
DSP
CVBS
SIF
Generation
I
2
C
IF In
Tuner
f
ref
TOP
A
D
A
D
AGC
A
D
A
D
Carri
er
Rec
ov
ery
F
ilter
ing
TAGC
VAGC
AAGC
EQU
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10 11
33 32 31 30 29 28 27 26 25 24 23
PORT2
PORT3
PORT4
ADR_SEL
PORT5
DVDD_ADC
DVSS_ADC
XTAL_IN
XTAL_OUT
VREF
SGND
AVSS_DAC
AVDD_DAC
SIF
REF_SW
CVBS
TEST2
TEST1
TEST0
SHIELD
AVSS_SYN
AVDD_SYN
PORT1
PORT0
DVSS_CAP
DVSS
DVDD
TUNER_AGC
DVDD_CAP
I2C_SCL
I2C_SDA
RESETQ
TEST_EN
AVDD_ADC
ANATSTX
ANATSTY
AVDD_FE8
AVSS_FE8
AVSS_ADC
AVSS_FE40
IFINX
AVDD_FE40
IFINY
AVSS_FE40
DRX 396xA
7.2. Pin Configuration
51
LC-20B6E
Pin No.
Pin Name
Type
Supply
Voltage
Connection
Short Description
(If not used)
1
AVSS_ADC
OBL
Analog ground for ADC
2
AVDD_ADC
OBL
Analog supply for ADC (+5 V)
3
ANATSTX
I/O
AVDD_FE8
GND
Test pin 
4
ANATSTY
I/O
AVDD_FE8
GND
Test pin
5
AVDD_FE8
OBL
2
nd
 analog supply for the front-end
6
AVSS_FE8
OBL
2
nd
 analog ground for the front-end
7
AVSS_FE40
OBL
1
st
 analog ground for the front-end
8
IFINX
IN
AVDD_FE40
OBL
IF input
9
AVDD_FE40
OBL
1
st
 analog supply for the front-end (+5 V)
10
IFINY
IN
AVDD_FE40
OBL
IF input
11
AVSS_FE40
OBL
1
st
 analog ground for the front-end
12
AVDD_SYN
OBL
Analog supply for synthesizer (+5 V)
13
AVSS_SYN
OBL
Analog ground for synthesizer
14
SHIELD
IN
OBL
Shield GND
15
TEST0
IN
AVDD_DAC
GND
Test Pin
16
TEST1
IN
AVDD_DAC
GND
Test Pin
17
TEST2
IN
AVDD_DAC
GND
Test Pin
18
CVBS
OUT AVDD_DAC OBL
CVBS 
output 
19
REF_SW
IN
AVDD_DAC
OBL
Reference frequency switch
20
SIF
OUT AVDD_DAC OBL
SIF 
output 
21
AVDD_DAC
OBL
DAC supply (+5 V)
22
AVSS_DAC
OBL
DAC ground
23
TEST_EN
IN DVDD 
GND
Test 
enable
24
RESETQ
IN
DVDD
OBL
Reset
25
I2C_SDA
I/O
DVDD
OBL
I
2
C data
26
I2C_SCL
I/O
DVDD
OBL
I
2
C clock
7.3. Pin Connections
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