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4. IC8701 (VHIAD9883A1-1) (See note on Source of Documentation Chapter, page 119)

I

nputs

R

AIN

Analog Input for Converter R

0.0 V to 1.0 V

54

G

AIN

Analog Input for Converter G

0.0 V to 1.0 V

48

B

AIN

Analog Input for Converter B

0.0 V to 1.0 V

43

HSYNC

Horizontal SYNC Input

3.3 V CMOS

30

VSYNC

Vertical SYNC Input

3.3 V CMOS

31

SOGIN

Input for Sync-on-Green

0.0 V to 1.0 V

49

CLAMP

Clamp Input (External CLAMP Signal)

3.3 V CMOS

38

COAST

PLL COAST Signal Input

3.3 V CMOS

29

Outputs

Red [7:0]

Outputs of Converter Red, Bit 7 is the MSB

3.3 V CMOS

70–77

Green [7:0]

Outputs of Converter Green, Bit 7 is the MSB

3.3 V CMOS

2–9

Blue [7:0]

Outputs of Converter Blue, Bit 7 is the MSB

3.3 V CMOS

12–19

DATACK

Data Output Clock

3.3 V CMOS

67

HSOUT

HSYNC Output (Phase-Aligned with DATACK)

3.3 V CMOS

66

VSOUT

VSYNC Output (Phase-Aligned with DATACK)

3.3 V CMOS

64

SOGOUT

Sync-on-Green Slicer Output

3.3 V CMOS

65

References

REF BYPASS

Internal Reference Bypass

1.25 V

58

MIDSCV

Internal Midscale Voltage Bypass

37

FILT

Connection for External Filter Components for Internal PLL

33

Power Supply

V

D

Analog Power Supply

3.3 V

39, 42,
45, 46, 51, 52,
59, 62

V

DD

Output Power Supply

3.3 V

11, 22, 23, 69,
78, 79

PV

D

PLL Power Supply

3.3 V

26, 27, 34, 35

GND

Ground

0 V

1, 10, 20, 21,
24, 25, 28, 32,
36, 40, 41, 44,
47, 50, 53, 60,
61, 63, 68, 80

Control

SDA

Serial Port Data I/O

3.3 V CMOS

57

SCL

Serial Port Data Clock (100 kHz Maximum)

3.3 V CMOS

56

A0

Serial Port Address Input 1

3.3 V CMOS

55

OUTPUTS

HSOUT

Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be pro-
grammed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.

VSOUT

Vertical Sync Output
A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial
bus bit. The placement and duration in all modes is set by the graphics transmitter.

SOGOUT

Sync-On-Green Slicer Output
This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the
Hsync input. See the Sync Processing Block Diagram (Figure 12) to view how this pin is connected. (Note: Besides
slicing off SOG, the output from this pin gets no other additional processing on the AD9883A. Vsync separation is performed
via the sync separator.)

SERIAL PORT (2-Wire)

SDA

Serial Port Data I/O

SCL

Serial Port Data Clock

A0

Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.

DATA OUTPUTS

RED

Data Output, Red Channel

GREEN

Data Output, Green Channel

BLUE

Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling  time is
changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also
moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figures 7, 8, and 9.

DATA CLOCK OUTPUT

DATACK

Data Output Clock
This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced  by the
internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed
by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.

INPUTS

R

AIN

Analog Input for Red Channel

G

AIN

Analog Input for Green Channel

B

AIN

Analog Input for Blue Channel
High impedance inputs that accept the Red, Green, and Blue channel graphics signals, respectively. (The three channels
are identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.

HSYNC

Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference
for pixel clock generation. The logic sense of this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used.
When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal
input threshold of 1.5 V.

VSYNC

Vertical Sync Input
This is the input for vertical sync.

SOGIN

Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is
connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage
threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a  noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync infor mation
that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left
unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.

CLAMP

External Clamp Input
This logic input may be used to define the time during which the input signal is clamped to ground. It should be exer-
cised when the reference dc level is known to be present on the analog input channels, typically during the back porch of
the graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1, (register 0FH, Bit 7, default is 0).
When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration  from
the trailing edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity register 0FH, Bit  6. When not
used, this pin must be grounded and Clamp Function programmed to 0.

COAST

Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing  a clock at
its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync
pulses during the vertical interval. The COAST signal is generally not required for PC-generated signals. The logic sense
of this pin is controlled by Coast Polarity (register 0FH, Bit 3). When not used, this pin may be grounded and Coast
Polarity programmed to 1, or tied HIGH (to V

D

through a 10 k

Ω resistor) and Coast Polarity programmed to 0. Coast

Polarity defaults to 1 at power-up.

REF BYPASS Internal Reference BYPASS

Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 

µF capacitor. The

absolute accuracy of this reference is 

±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9883A

applications. If higher accuracy is required, an external reference may be employed instead.

MIDSCV

Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 

µF capacitor. The

exact voltage varies with the gain setting of the Blue channel.

FILT

External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to
this pin. For optimal performance, minimize noise and parasitics on this node.

POWER SUPPLY

V

D

Main Power Supply
These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible.

V

DD

Digital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients
(noise). These supply pins are identified separately from the V

D

pins so special care can be taken to minimize output

noise transferred into the sensitive analog circuitry. If the AD9883A is interfacing with lower voltage logic, V

DD

may be

connected to a lower supply voltage (as low as 2.5 V) for compatibility.

PV

D

Clock Generator Power Supply
The most sensitive portion of the AD9883A is the clock generation circuitry. These pins provide power to the clock PLL and
help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

GND

Ground
The ground return for all circuitry on-chip. It is recommended that the AD9883A be assembled on a single solid ground
plane, with careful attention given to ground current paths.