Sharp LC-20B6E (serv.man10) Service Manual ▷ View online
52
LC-20B6E
27
DVDD_CAP
OBL
Digital supply capacitor
28
DVDD
OBL
Digital supply (+3.3 V)
29
DVSS
OBL
Digital ground
30
DVSS_CAP
OBL
Digital capacitor ground
31
PORT0
OUT
DVDD
LV
Digital output port
32
PORT1
OUT
DVDD
LV
Digital output port
33
TUNER_AGC
OUT
DVDD
OBL
Tuner AGC current output
34
PORT2
OUT
DVDD
LV
Digital output port
35
PORT3
OUT
DVDD
LV
Digital output port
36
PORT4
OUT
DVDD
LV
Digital output port
37
ADR_SEL
IN DVDD
OBL
Address
select
38
PORT5
OUT
DVDD
LV
Digital output port
39
DVDD_ADC
OBL
Digital supply for ADC (+3.3 V)
40
DVSS_ADC
OBL
Digital ground for ADC
41
XTAL_IN
IN
AVDD_ADC
OBL
Crystal oscillator
42
XTAL_OUT
I/O
AVDD_ADC
OBL
Crystal oscillator /
external reference frequency
external reference frequency
43
VREF
AVDD_ADC
OBL
ADC reference voltage
44
SGND
AVDD_ADC
OBL
ADC reference ground
Pin No.
Pin Name
Type
Supply
Voltage
Voltage
Connection
Short Description
(If not used)
7.3. Pin Connections (Continued)
53
LC-20B6E
Pin 1, AVSS_ADC
− Analog ground for ADC
Pin 2, AVDD_ADC
− Analog supply for ADC
This pin must be connected to 5 V.
Pin 3, ANATSTX
− Reserved for test
This pin should be connected to analog ground.
Pin 4, ANATSTY
− Reserved for test
This pin should be connected to analog ground.
Pin 5, AVDD_FE8
− Analog supply for analog front-
end. This pin must be connected to 5 V.
Pin 6, AVSS_FE8
− Analog ground for analog front-
end
Pin 7, AVSS_FE40
− Analog ground for IF input
circuitry.
The layout of the IF input should be symmetrical to
AVDD_FE40.
The layout of the IF input should be symmetrical to
AVDD_FE40.
Pin 8, IFINX
− Balanced IF input X
This pin must be connected to SAW output. SAW has
to be placed as close as possible. The layout of the IF
input should be symmetrical to AVDD_FE40.
to be placed as close as possible. The layout of the IF
input should be symmetrical to AVDD_FE40.
Pin 9, AVDD_FE40
− Analog supply for IF input cir-
cuitry
This pin must be connected to 5 V. The layout of the IF
input should be symmetrical to AVDD_FE40.
This pin must be connected to 5 V. The layout of the IF
input should be symmetrical to AVDD_FE40.
Pin 10, IFINY
− Balanced IF input Y
This pin must be connected to SAW output. SAW has
to be placed as close as possible. The layout of the IF
input should be symmetrical to AVDD_FE40.
to be placed as close as possible. The layout of the IF
input should be symmetrical to AVDD_FE40.
Pin 11, AVSS_FE40
− Analog ground for IF input cir-
cuitry
The layout of the IF input should be symmetrical to
AVDD_FE40.
The layout of the IF input should be symmetrical to
AVDD_FE40.
Pin 12, AVDD_SYN
− Analog supply for clock synthe-
sizer. This pin must be connected to 5 V.
Pin 13, AVSS_SYN
− Analog ground for clock synthe-
sizer.
Pin 14, SHIELD
− Analog ground for shielding analog
from digital part.
Pin 15,16,17, TEST0 1 2
− Pins for factory test
Pin 18, CVBS
− Video output
Output level is set via I
2
C-Bus. An appropriate video
processor (e.g. VPC etc.) has to be connected to that
pin.
pin.
Pin 19, REF_SW
− Reference frequency switch.
This input defines the default setting of the reference
divider after POR. For 20.25 MHz applications it has to
be connected to ground, for applications with higher
frequencies than 20.25 MHz it must be connected to
3.3 V.
divider after POR. For 20.25 MHz applications it has to
be connected to ground, for applications with higher
frequencies than 20.25 MHz it must be connected to
3.3 V.
Pin 20, SIF
− sound IF output
Output level is set via I2C-Bus. An appropriate sound
processor (e.g. MSP) has to be connected to that pin.
processor (e.g. MSP) has to be connected to that pin.
Pin 21, AVDD_DAC
− Analog supply for the analog
output DACs
This pin must be connected to 5 V.
This pin must be connected to 5 V.
Pin 22, AVSS_DAC
− Analog Ground for the analog
output DACs
This pin must be connected to ground.
This pin must be connected to ground.
Pin 23, TEST_EN
− Test Enable pin
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
tion it must be connected to ground.
Pin 24, RESET
− Reset input
For normal operation, a high level is required. A low
level resets the DRX 396xA.
level resets the DRX 396xA.
Pin 25, 26, I2C_SDA, I2C_SCL
− I
2
C control bus data
and clock
Pin 27, DVDD_CAP
− Digital supply pin
This pin has to be connected to 3.3 V according to the
application circuit.
application circuit.
Pin 28, DVDD
− Digital supply pin
This pin has to be connected to 3.3 V according to the
application circuit.
application circuit.
Pin 29, DVSS
− Digital ground pin
This pin has to be connected to digital ground accord-
ing to the application circuit.
ing to the application circuit.
Pin 30, DVSS_CAP
− Digital ground pin
This pin has to be connected according to the applica-
tion circuit.
tion circuit.
Pin 31, 32, 34, 35, 36, 38, PORT0 1 2 3 4 5
− General
purpose output ports
Their states are controlled via I2C bus.
Their states are controlled via I2C bus.
Pin 33, TUNER_AGC
−
This pin controls the delayed tuner AGC. As it is a
noise-shaped-I-DAC output, it has to be connected
according to the application circuit.
noise-shaped-I-DAC output, it has to be connected
according to the application circuit.
Pin 37, ADR_SEL
− I
2
C Bus address select
By means of this pin, one of three device addresses
can be selected.
can be selected.
Pin 39, DVDD_ADC
− Digital supply pin for ADC
This pin has to be connected to 3.3 V.
7.4. Pin Descriptions
54
LC-20B6E
Pin 40, DVSS_ADC
− Digital ground pin for ADC
This pin has to be connected to digital ground.
Pin 41, XTAL_IN
− Crystal input pin
If an external clock is used this pin should be left open.
A crystal should be placed as close as possible to this
pin. External capacitors at each crystal pin to ground
are required. It should be verified by layout, that no
supply current is flowing through the ground connec-
tion point.
A crystal should be placed as close as possible to this
pin. External capacitors at each crystal pin to ground
are required. It should be verified by layout, that no
supply current is flowing through the ground connec-
tion point.
Pin 42, XTAL_OUT
− Crystal output pin
If an external clock is used, it has to be connected to
this pin. A crystal should be placed as close as possi-
ble to this pin. External capacitors at each crystal pin
to ground are required. It should be verified by layout,
that no supply current is flowing through the ground
connection point.
this pin. A crystal should be placed as close as possi-
ble to this pin. External capacitors at each crystal pin
to ground are required. It should be verified by layout,
that no supply current is flowing through the ground
connection point.
Pin 43, VREF
− Analog reference voltage
This pin must be connected to SGND via a circuitry
according to the application circuit.
according to the application circuit.
Pin 43, SGND
− Reference for analog ground
This pin must be connected separately to a single
ground point.
ground point.
7.4. Pin Descriptions (Continued)
55
LC-20B6E
8. IC3403 VHISM5301AS-1
8.1. Pinout
MUXSEL
1
SYNCIN
2
VCC4
3
R
INA
/Y
INA
4
GSR1
5
R
INB
/Y
INB
6
NC
7
G
INA
/U
INA
8
GSG1
9
G
INB
/U
INB
10
NC
11
B
INA
/V
INA
12
28
27
26
25
24
23
22
21
20
19
18
17
VFC
RFC
GND4
VCC1
R
OUT
/Y
OUT
GND1
VCC2
G
OUT
/U
OUT
GND2
VCC3
B
OUT
/V
OUT
GND3
13
14
16
15
GSB1
B
INB
/V
INB
DISABLE
NC
GND
GND
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