Sharp 32JF-77 (serv.man15) Service Manual ▷ View online
61
32JF-77H
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6
BLOCK DIAGRAM
handbook, full pagewidth
MHC108
DIGITAL VCO CONTROL
AFC DETECTOR
RC VCO
VIF-PLL
VIF-AGC
TUNER AGC
SUPPLY
SIF AGC
AUDIO PROCESSING
AND SWITCHES
NARROW-BAND
FM-PLL DEMODULATOR
SINGLE REFERENCE QSS MIXER
INTERCARRIER MIXER
AND AM DEMODULATOR
SOUND TRAPS
4.5 to 6.5 MHz
TAGC
C
VAGC(pos)
C
AGC(neg)
C
BL
VAGC
(1)
TOP
14 (15)
VPLL
19 (21)
9 (8)
16
15 (16)
21 (23)
4 (2)
10 (9)
11 (10)
12 (11)
18 (20)
20 (22)
2 (31)
1 (30)
(18) 17
(7) 8
(3) 5
(4) 6
external reference signal
or 4 MHz crystal
REF
AFC
AUD
CVBS
audio output
video output
: 2 V (p-p)
[1.1 V (p-p) without trap]
C
AF
SIOMAD
SDA
SCL
MAD
V
P
C
AGC
(6, 12, 13, 14, 17,
19, 25, 28, 29, 32)
13
n.c.
AGND
7 (5)
DGND
OUTPUT
PORTS
I
2
C-BUS TRANSCEIVER
22 (24)
3 (1)
OP1
OP2
FMPLL
DEEM
AFD
sound intercarrier output
and MAD select
FM-PLL
filter
VIF-PLL
filter
de-emphasis
network
VIF2
VIF1
24 (27)
23 (26)
SIF2
SIF1
TDA9885
TDA9886
Fig.1 Block diagram.
(1)
Not connected for TDA9885.
Pin numbers for TDA9885HN in parenthesis.
TDA9886 (IC201)
Block Diagram
62
32JF-77H
7
PINNING
SYMBOL
PIN
DESCRIPTION
TDA9886T
TDA9886TS
TDA9885T
TDA9885TS
TDA9885HN
VIF1
1
1
30
VIF differential input 1
VIF2
2
2
31
VIF differential input 2
n.c.
−
−
32
not connected
OP1
3
3
1
output port 1; open-collector
FMPLL
4
4
2
FM-PLL for loop filter
DEEM
5
5
3
de-emphasis output for capacitor
AFD
6
6
4
AF decoupling input for capacitor
DGND
7
7
5
digital ground
n.c.
−
−
6
not connected
AUD
8
8
7
audio output
TOP
9
9
8
tuner AGC TakeOver Point (TOP) for resistor adjustment
SDA
10
10
9
I
2
C-bus data input and output
SCL
11
11
10
I
2
C-bus clock input
SIOMAD
12
12
11
sound intercarrier output and MAD select with resistor
n.c.
−
−
12
not connected
n.c.
13
13
13
not connected
n.c.
−
−
14
not connected
TAGC
14
14
15
tuner AGC output
REF
15
15
16
4 MHz crystal or reference signal input
VAGC
16
−
−
VIF-AGC for capacitor
n.c.
−
16
17
not connected
CVBS
17
17
18
composite video output
n.c.
−
−
19
not connected
AGND
18
18
20
analog ground
VPLL
19
19
21
VIF-PLL for loop filter
V
P
20
20
22
supply voltage
AFC
21
21
23
AFC output
OP2
22
22
24
output port 2; open-collector
n.c.
−
−
25
not connected
SIF1
23
23
26
SIF differential input 1 and MAD select with resistor
SIF2
24
24
27
SIF differential input 2 and MAD select with resistor
n.c.
−
−
28
not connected
n.c.
−
−
29
not connected
handbook, halfpage
TDA9885TS
TDA9886TS
TDA9886TS
MHC110
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMAD
SIF2
SIF1
OP2
AFC
VP
VPLL
AGND
CVBS
VAGC
(1)
REF
TAGC
n.c.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Fig.3 Pin configuration for SSOP24.
(1) Not connected for TDA9885TS.
TDA9886 (IC201)
Pin Description
Pin Assignments
63
32JF-77H
Sourc
e Select
L
oud
-
SCA
RT1
SCA
RT2
SCA
RT1
SCA
RT2
SCA
RT4
SCA
RT3
MONO
De
-
m
o
d
u
lat
or
H
e
adp
ho
ne/
I
2
S
So
un
d
Pr
oc
ess
in
g
sp
eak
er
S
oun
d
P
roc
es
s
ing
DAC
DAC
ADC
Lo
ud-
DAC
DAC
ADC
Su
bwo
ofer
I
2
S1
I
2
S2
S
o
u
nd I
F
1
S
o
u
nd I
F
2
sp
ea
ker
H
e
ad
ph
o
n
e
Su
rr
ou
nd
Pr
e
-
pr
oc
e
s
s
in
g
Pr
es
ca
le
Pr
es
cale
SCA
RT
DSP
Inpu
t
Se
le
ct
SC
A
R
T
O
u
tput
Se
le
ct
I
2
S3
MSP4410G (IC303)
Block Diagram
64
32JF-77H
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP
AVSUP
ANA_IN1+
ANA_IN
−
ANA_IN2+
TESTEN
XTAL_IN
XTAL_OUT
TP
AUD_CL_OUT
NC
NC
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
STANDBYQ
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R
NC
NC
DACM_SUB
NC
DACM_L
DACM_R
VREF2
DACA_L
NC
AVSS
AVSS
MONO_IN
NC
VREFTOP
SC1_IN_R
SC1_IN_L
ASG
NC
SC2_IN_R
SC2_IN_L
ASG
SC3_IN_R
SC3_IN_L
ASG
SC4_IN_R
SC4_IN_L
NC
AGNDC
AHVSS
AHVSS
NC
NC
I2C_CL
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
ADR_CL
NC
DVSUP
DVSUP
DVSUP
DVSS
DVSS
DVSS
I2S_DA_IN2
NC
I2S_CL3
I2S_WS3
RESETQ
I2S_DA_IN3
NC
DACA_R
MSP 44x0G
MSP4410G (IC303)
Pin Assignments
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