DOWNLOAD Sharp 32JF-77 (serv.man15) Service Manual ↓ Size: 6.53 MB | Pages: 96 in PDF or view online for FREE

Model
32JF-77 (serv.man15)
Pages
96
Size
6.53 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / CTR
File
32jf-77-sm15.pdf
Date

Sharp 32JF-77 (serv.man15) Service Manual ▷ View online

65
32JF-77H
18W  OUTPUT POWER:
R
L
 = 8
Ω/4Ω; THD = 10%
HIGH EFFICIENCY
WIDE SUPPLY VOLTAGE RANGE (UP TO
±25V)
SPLIT SUPPLY
OVERVOLTAGE PROTECTION
ST-BY AND MUTE FEATURES
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
DESCRIPTION
The TDA7481 is an audio class-D amplifier as-
sembled in Multiwatt15 package specially de-
signed for high efficiency applications mainly for
TV and Home Stereo sets.
ORDERING NUMBER: TDA7481
Multiwatt15
TDA7481L (IC501)
Pin Assignments
Pin Description
1
2
3
4
5
6
7
9
10
11
8
+V
CC SIGN
ST-BY/MUTE
IN
-V
CC SIGN
SGN-GND
FREQ
FEEDCAP
N.C.
BOOT
BOOTDIODE
OUT
TAB CONNECTED TO PIN 8
13
14
15
12
-V
CC POW
-V
CC POW
+V
CC POW
VREG
D96AU535A
N.
Name
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT
BOOTDIODE
BOOT
NC
FEEDCAP
FREQ
SGN-GND
–V
CC 
SIGN
IN
ST-BY/MUTE
+V
CC 
SIGN
VREG
+V
CC
 POW
-V
CC
 POW
-V
CC
 POW
PWM OUTPUT 
BOOTSTRAP DIODE ANODE
BOOTSTRAP
NOT CONNECTED
FEEDBACK INTEGRATING CAPACITOR
SETTING FREQUENCY RESISTOR 
SIGNAL GROUND
SIGNAL  NEGATIVE SUPPLY
INPUT
CONTROL STATE PIN
POSITIVE SIGNAL SUPPLY
INTERNAL VOLTAGE REGULATOR
POSITIVE POWER SUPPLY
NEGATIVE POWER SUPPLY (to be connected to pin 13 via CS)
NEGATIVE POWER SUPPLY (to be connected to pin 13 via CS)
66
32JF-77H
SYMBOL
PIN
DESCRIPTION
V
ip
1
non-inverting voltage input
V
DDL
2
supply voltage LOW
V
in
3
inverting voltage input
GND
4
ground, substrate
I
om
5
black current measurement
output
V
DDH
6
supply voltage HIGH
V
cn
7
cathode transient voltage output
V
oc
8
cathode DC voltage output
V
fb
9
feedback voltage output
Fig.2  Pin configuration.
ndbook, halfpage
MGA057
1
2
3
4
5
6
7
8
9
DDL
V
GND
TDA6111Q
ip
V
in
V
om
I
oc
V
cn
V
fb
V
DDH
V
TDA6111Q (IC850, IC851, IC852)
Block Diagram
Pin Description
Pin  Assignments
Fig.1  Block diagram.
handbook, full pagewidth
DIFFERENTIAL
STAGE
MIRROR
MIRROR
CURRENT
SOURCE
MIRROR
MIRROR
TDA6111Q
7 V
supply voltage
input HIGH
feedback
output
6
Vbias
FOLLOWERS
C par
9
non-inverting
input
inverting
input
3
1
4
2
ground
(substrate)
supply voltage
input LOW
7
8
5
cathode
transient
output
cathode
DC output
black current
measurement
output
MGA058
67
32JF-77H
SDA 6000 (IC6001)
 
Type
Package
SDA 6000 / SDA 6001
P-MQFP-128-2
Teletext Decoder with Embedded 16-bit Controller
M2
Version 3.00
CMOS
P-MQFP-128-2
1.1
Features
General
• Level 1.5, 2.5, 3.5 WST Display Compatible
• Fast  External  Bus  Interface  for  SDRAM  (Up  to
8 MByte)  and  ROM  or  Flash-ROM  (Up  to  2  x
4 MByte)
• Embedded General Purpose 16 Bit CPU (Also used
as TV-System Controller, C16x Compatible)
• Display Generation Based on Pixel Memory
• Program  Code  also  Executable  From  External
SDRAM
• Embedded Refresh Controller for External SDRAM
• Enhanced Programmable Low Power Modes
• Single 6 MHz Crystal Oscillator
• Multinorm H/V-Display Synchronization in Master or Slave Mode 
• Free Programmable Pixel Clock from 10 MHz to 50 MHz
• Pixel Clock Independent from CPU Clock
• 3
× 6 Bits RGB-DACs On-Chip
• Supply Voltage 2.5 and 3.3 V
• P-MQFP-128 Package
Microcontroller Features
• 16-bit C166-CPU Kernel (C16x Compatible)
• 60 ns Instruction Cycle Time
• 2 KBytes Dual Ported IRAM
• 2 KBytes XRAM On-chip
• General Purpose Timer Units (GPT1 and GPT2). 
• Asynchronous/Synchronous  Serial  Interface  (ASC0)  with  IrDA  Support.  Full-duplex
Asynchronous Up To 2 MBaud or Half-duplex Synchronous up to 4.1 MBaud.
68
32JF-77H
SDA 6000 (IC6001)
 
• High-speed Synchronous Serial Interface (SSC). Full- and Half-duplex synchronous
up to 16.5 Mbaud
• 3 Independent, HW-supported Multi Master/Slave I
2
C Channels at 400 Kbit/s
• 16-Bit Watchdog Timer (WDT)
• Real Time Clock (RTC)
• On Chip Debug Support (OCDS)
• 4-Channel 8-bit A/D Converter
• 42 Multiple Purpose Ports
• 8 External Interrupts
• 33 Interrupt Nodes
Display Features
• OSD size from 0 to 2046 (0 to 1023) pixels in horizontal (vertical) direction
• Frame Buffer Based Display
• 2 HW Display Layers
• Support of Double Page Level 2.5 TTX in 100 Hz Systems
• Support of Transparency for both Layers Pixel by Pixel
• User Programmable Pixel Frequency from 10.0 MHz to 50 MHz
• Up to 65536 Displayable Colors in one Frame
• DMA Functionality
• Graphic Accelerator Functions (Draw Lines, Draw and Fill Rectangle, etc.)
• 1, 2, 4 or 8-bit Bitmaps (up to 256 out of 4096 colors)
• 12 bit/16 bit RGB Mode for Display of up to 65535 Colors
• HW-support for Proportional Characters
• HW-support for Italic Characters
• User Definable Character Fonts
• Fast Blanking and Contrast Reduction Output
• Double resolution graphic for interlaced sync rasters (SDA6001 only)
Acquisition Features
• Two Independent Data Slicers (One Multistandard Slicer + one WSS-only Slicer)
• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)
• Four Different Framing Codes Available
• Data Caption only Limited by available Memory
• Programmable VBI-buffer
• Full Channel Data Slicing Supported
• Fully Digital Signal Processing
• Noise Measurement and Controlled Noise Compensation
• Attenuation Measurement and Compensation
• Group Delay Measurement and Compensation
• Exact Decoding of Echo Disturbed Signals
Page of 96
Display

Click on the first or last page to see other 32JF-77 (serv.man15) service manuals if exist.