Sharp AR-155 (serv.man13) Service Manual ▷ View online
Table A (Signals used in the FAX PWB)
PIN No.
(CN5)
Signal
name
IN/OUT
Descriptions
3
/SCLINE
OUT
Effective input image area
6
FTXD
OUT
Serial communication data
7
/FRTS
OUT
Serial reception ready
(Machine side)
(Machine side)
12
/F-RESET
OUT
Reset signal
13
/HSYNC
OUT
Horizontal sync signal
14
∼ 21,
44
∼ 51
OUTD1
∼
OUTD15
OUT
Data to the expanded PWB
24
/FAXREQ
OUT
Data transfer REQ signal
25
/FAXCS
IN
OUTD bus enable signal
33
/PRLINE
OUT
Effective print area
34
/FPAGE
IN
Page data READY
35
/FREADY
IN
FAX PWB recognition signal
36
/READY
OUT
READY signal on the
machine side
machine side
37
FRXD
IN
Serial communication data
38
/FCTS
IN
Serial reception READY
(FAX side)
(FAX side)
43
/POFF
OUT
Power OFF signal
54
/FAXPRD
IN
Video data from FAX PWB
55
/FAXACK
IN
Data transfer ACK signal
Table B (Signals used in PCL PWB)
PIN No.
(CN5)
Signal
name
IN/OUT
Descriptions
5
/PREADY
IN
PCL PWB recognition signal
6
FTXD
OUT
Serial communication data
7
/FRTS
OUT
Serial reception READY
(Machine side)
(Machine side)
12
/F-RESET
OUT
Reset signal
13
/HSYNC
OUT
Horizontal sync signal
34
/FPAGE
IN
Page data READY
36
/READY
OUT
READY signal on the
machine side
machine side
37
FRXD
IN
Serial communication data
38
/FCTS
IN
Serial reception READY
(PCL side)
(PCL side)
52
/PCLPRD
IN
Video data from PCL PWB
(4) 1284/USB circuit select control section
The GDI/USB PWB is connected to CN15 connector to control switch-
ing between IEEE1284 port and USB port.
If USB cable isn’t connected to the GDI/USB PWB, the /1284-EN signal
becomes LOW to allow the user of IEEE1284 port.
ing between IEEE1284 port and USB port.
If USB cable isn’t connected to the GDI/USB PWB, the /1284-EN signal
becomes LOW to allow the user of IEEE1284 port.
If USB cable is connected, the /USB-EN signal becomes LOW to allow
the use of USB port.
Since USB has priority, when USB cable is connected, it is selected.
That is, when USB cable is connected, IEEE1284 port (parallel port) is
disabled.
the use of USB port.
Since USB has priority, when USB cable is connected, it is selected.
That is, when USB cable is connected, IEEE1284 port (parallel port) is
disabled.
USB-IN
/1284-EN
USB-ON
/USB-EN
/GDI-IN
/ACK
PARAAD5
SLCT
PARAAD6
PARAAD7
/STB
PARAAD1
/REV
PARAAD3
PARAAD0
INIT
BUSY
/SLCTIN
/AUTOFD
PE
/FAULT
PARAAD2
PARAAD4
3.3V
5V
31FT-BT-VK-N
CN15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(5-A3)
(5-A3)
(1-B1)
(5-A3)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(2-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D2)
(5-D2)
GDI/USB CN
AR-F151
11 – 12
117
HBE
118
ADS
119
DDIN
120
AD0
121
AD1
122
AD2
123
AD3
124
AD4
125
VCCD9
126
AD5
127
AD6
128
AD7
129
AD8
130
AD9
131
GNDD9
132
AD10
1
AD11
2
AD12
3
AD13
4
AD14
5
VCCD1
6
AD15
7
A16
8
A17
9
A18
10
A19
11
GNDD1
12
A20
13
A21
14
A22
15
A23
16
PDO
17
VCCD2
83
VCCA2
82
GNDA2
81
PTMP
80
SBG
79
SCVO
78
SVI
77
GNDA1
76
VCCA1
75
GNDD5
74
PMPH0
73
PMPH1
72
PMPH2
71
PMPH3
70
SMPH0
69
SMPH1
68
SMPH2
67
SMPH3
66
VCCD5
65
PEXT
64
PFAIL
63
SOSCO
62
SOSCI
61
RST
60
WDT
59
BUZCLK
58
DMRQ3
57
MWSI
56
URXD
55
UTEN
54
PIO0
53
PIO1
52
SNH
51
GNDD4
18
SD
F
D
B
K
19
SD
IN
20
SD
O
U
T
21
SL
S
22
SC
L
K
1
23
SP
D
W
24
MW
S
K
25
G
NDD2
26
DMA
K
3
27
SD
IS
28
DMA
K
1
29
SC
L
K
2
30
ST
B
3
31
ST
B
2
32
V
CCD3
33
CTTL
34
ST
B1
35
ST
B0
36
FO
S
C
I
37
FO
S
C
O
38
G
NDD3
39
CCL
K
40
IN
T
0
41
IN
T
1
42
IN
T
2
43
IN
T
3
44
IN
T
R
45
URE
N
46
UTX
D
47
MWS
O
48
S
BYPS
49
PC
L
K
50
V
CCD4
TL/EE/11331-54
116
G
NDD8
115
HO
LD
114
HL
CA
113
WE
0
112
WE
1
111
OE
110
SE
L1
109
VC
C
D
8
108
SEL0
107
SEL3
106
RA
S
0
105
RA
S
1
104
CA
S
103
CW
A
IT
102
G
NDD7
101
MA
1
100
MA
2
99
MA
3
98
MA
4
97
MA
5
96
V
CCD7
95
MA
6
94
MA
7
93
MA
8
92
MA
9
91
MA
10
90
G
NDD6
89
MA
11
88
MA
12
87
MA
13
86
MA
14
85
MA
15
84
V
CCD6
132-Pin FQFP Package
3. FAX PWB Functional block diagram (AR-F151 only)
4. LSI pin layout (AR-F151 only)
(1) NSFX200 (IC503) pin layout
Speaker
LCD PWB
PWB
Prog.ROM
CPU Bus
FX164
Image.
Memory
Memory
LC8213
Image. Bus
ASIC
Buf. Mem.
Main Memory
FX200
NCU
PSTN
PCL/FAX MCU
LZ9FH19
SCAN
DATA
Memory
DATA
Memory
PRINT DATA
AR-F151
11 – 13
NSFX200 (IC503) supplies
Signal
Pin Numbers
Descrlption
GNDA1
∼ 2
77
82
Analog ground.
GNDD1
∼ 9
11 25 38
51 75 90
102 116 131
51 75 90
102 116 131
Digital ground.
VCCA1
∼ 2
76
83
Analog Power — 5V supply
for analog circuits.
for analog circuits.
VCCD1
∼ 9
5 17 32
50 66 84
96 109 125
50 66 84
96 109 125
Digital Power — 5V supply
for digital circuits.
for digital circuits.
Input Signals
Signal
Pin Numbers
Description
CTTL
33
CPU Clock — CPU clock that
is used for clocking the
NS32FX200.
is used for clocking the
NS32FX200.
DMRQ3
58
DMA Request — Input for
DMA channel 3 request.
DMA channel 3 request.
FOSCI
36
High-Speed Oscillator —
(49.1520 MHz) Asynchronous.
When an external oscillator is
used, FOSCO should be left
unconnected or loaded with
no more than 5 pF of stray
capacitance.
(49.1520 MHz) Asynchronous.
When an external oscillator is
used, FOSCO should be left
unconnected or loaded with
no more than 5 pF of stray
capacitance.
HBE
117
High Byte Enable — Status
signal used to enable data
transfers on the most
significant byte of the data bus.
signal used to enable data
transfers on the most
significant byte of the data bus.
HLDA
114
Hold Acknowledge — Issued
by the CPU to indicate it has
released the bus in response
to a HOLD request.
by the CPU to indicate it has
released the bus in response
to a HOLD request.
INT0
∼ 3
40 41 42
43
43
Interrupt In — Asynchronous.
External maskable prioritized
interrupt requests.
External maskable prioritized
interrupt requests.
MWSI
57
General purpose input pin.
PFAIL
64
Power Fall Indication — An
asynchronous signal which
forces the NS32FX 200 into
freeze mode.
asynchronous signal which
forces the NS32FX 200 into
freeze mode.
PTMP
81
Not used.
RST
61
Reset In — Asynhronous
reset input from the CPU.
reset input from the CPU.
SBG
80
Not used.
SDIN
19
Sigma-Delta Data In —
Asynchronous input from the
SDC analog receiver.
Asynchronous input from the
SDC analog receiver.
SOSCI
62
Low-Speed Oscillator —
(3.2768 kHz or 455 kHz)
Asynchronous. When an
external oscillator is used,
SOSCO should be left
unconnected or loaded with
no more than 5 pF of stray
capacitance.
(3.2768 kHz or 455 kHz)
Asynchronous. When an
external oscillator is used,
SOSCO should be left
unconnected or loaded with
no more than 5 pF of stray
capacitance.
SVI
78
Scanner Video In — Analog
current from the scanner
sample and hold circuit.
current from the scanner
sample and hold circuit.
URXD
56
UART Recelve —
Asynchronous input or general
purpose input pin.
Asynchronous input or general
purpose input pin.
UTEN
55
General purpose input pin.
Output Signals
Signal
Pin Numbers
Description
BUZCLK
59
Buzzer Clock —
Programmable frequency
clock for the buzzer.
Programmable frequency
clock for the buzzer.
CAS
104
DRAM Column Address
Strobe — Column address
strobe for DRAM banks
refresh.
Strobe — Column address
strobe for DRAM banks
refresh.
CCLK
39
CPU Double Clock — Feeds
CPU’S OSCIN. Asynchronous.
CPU’S OSCIN. Asynchronous.
CWAIT
103
Continuous Walt — Low
extends the memory cycle of
the CPU.
extends the memory cycle of
the CPU.
DMAK1
28
General purpose output pin.
DMAK3
26
DMA Acknowledge —
Output for DMA channel 3
acknowledge or general
purpose output pin.
Output for DMA channel 3
acknowledge or general
purpose output pin.
FOSCO
37
High-Speed Oscillator Out —
Asynchronous.This line is
used as the return path for
the crystal (if used).
Asynchronous.This line is
used as the return path for
the crystal (if used).
HOLD
115
Hold Request — When low,
HOLD requests the bus from
the CPU to perform DMA
operations or to insert idle
bus cycles.
HOLD requests the bus from
the CPU to perform DMA
operations or to insert idle
bus cycles.
INTR
44
Interrupt Request — Low
indicates that an interrupt
request is being output to the
CPU.
indicates that an interrupt
request is being output to the
CPU.
MA1
∼ 15
101 100 99
98 97 95
94 93 92
91 89 88
87 86 85
98 97 95
94 93 92
91 89 88
87 86 85
Memory Address Bus —
Multiplexed DRAM address.
Multiplexed DRAM address.
MWSK
24
General purpose output pin.
OE
111
Output Enable — Used by
the addressed device to gate
the data onto the data bus.
the addressed device to gate
the data onto the data bus.
PDO
16
Not used.
PEXT
65
Not used.
PMPH0
∼ 3
74 73 72
71
71
Output port.
RAS0
106
DRAM Row Address
Strobes — Row address
strobe for DRAM banks 0
and 1.
Strobes — Row address
strobe for DRAM banks 0
and 1.
RAS1
105
RAS1 is not used.
SCLK1
22
General purpose output pin.
SCLK2/DAMK0
29
Scanner Clock 2 — Output,
DMA Acknowledge-output for
DMA channel 0 acknowledge.
DMA Acknowledge-output for
DMA channel 0 acknowledge.
SCVO
79
Scanner Compensated
Video Out — Analog current
for use by ABC or optional
video enhanement circuit.
Video Out — Analog current
for use by ABC or optional
video enhanement circuit.
SDFDBK
18
Sigma-Delta Feedback —
Feedback input to the SDC
analog receiver.
Asynchronous output signal.
Feedback input to the SDC
analog receiver.
Asynchronous output signal.
AR-F151
11 – 14
Signal
Pin Numbers
Description
SDIS/DMAK2
27
General purpose output pin.
SDOUT
20
Sigma-Delta Data Out —
Input to the SDC analog
transmitter.
Input to the SDC analog
transmitter.
SEL0
108
Zone Select — Used to
adderss the device according
to the selected zone.
adderss the device according
to the selected zone.
SEL1
110
SEL3
107
SLS
21
General purpose output pin.
SMPH0
∼ 3
70 69 68
67
67
Output port.
SOSCO
63
Low-Speed Oscillator Out —
Asynchronous. This line is
used as the return path for
the crystal (if used).
Asynchronous. This line is
used as the return path for
the crystal (if used).
SPDW
23
General purpose output pin.
STB0-3
35 34 31
30
30
General purpose output pin.
WDT
60
WATCHDOG Trap — Traps
CPU execution when
WATCHDOG detects error.
CPU execution when
WATCHDOG detects error.
WEO
113
Write Enable — Used by the
addressed device to get the
data from the data bus.WE0
for even and WE1 for odd
bytes.
addressed device to get the
data from the data bus.WE0
for even and WE1 for odd
bytes.
WE1
112
Input/Output Signals
Signal
Pin Numbers
Description
A16
∼ 23
7 8 9
10 12 13
14 15
10 12 13
14 15
High Order Address Bus —
The most significant eight bits
of the CPU address bus.
The most significant eight bits
of the CPU address bus.
AD0
∼ 15
120 121 122
123 124 126
127 128 129
130 132 1
2 3 4
6
123 124 126
127 128 129
130 132 1
2 3 4
6
Address/Data bus —
Multiplexed address/data
information.
Multiplexed address/data
information.
ADS
118
Address Strobe — Controls
memory access, and signals
the beginning of a bus cycle.
memory access, and signals
the beginning of a bus cycle.
DDIN
119
Data Direction In —
Indicates the direction of data
transfer during a bus cycle.
Indicates the direction of data
transfer during a bus cycle.
MWSO
47
General purpose I/O pin.
PCLK/DMRQ1
49
General purpose I/O pin.
PIO0-1
54 53
General Purpose I/O Pins.
SBYPS/DMRQ2
48
General purpose I/O pin.
SNH/DMRQ0
52
Sample and Hold — Output
to scanner sample and hold
circuit or DMA Request-input
for DMA channel 0 reques.
to scanner sample and hold
circuit or DMA Request-input
for DMA channel 0 reques.
UREN
45
General purpose I/O pin.
UTXD
46
UART Transmit — Output.
(2) NS32FX164 (IC507)
Supplles
V
V
CC
Power
+5 V positive supply.
+5 V positive supply.
GND
Ground.
Ground reference for both on-chip logic and output
drivers.
Ground reference for both on-chip logic and output
drivers.
Input Signals
RSTI
RSTI
Reset Input.
Schmitt triggered, asynchronous signal used to generate a
CPU reset.
Note: The reset signal is a true asynchronous input.
Schmitt triggered, asynchronous signal used to generate a
CPU reset.
Note: The reset signal is a true asynchronous input.
Therefore, no external synchronizing circuit is
needed.
needed.
HOLD
Hold Request.
When active, causes the CPU to release the bus for DMA
or multiprocessing purposes.
Note: If the HOLD signal is generated asynchronously, its
When active, causes the CPU to release the bus for DMA
or multiprocessing purposes.
Note: If the HOLD signal is generated asynchronously, its
set up and hold times may be violated. In this case,
it is recommended to synchronize it with CTTL to
minimize the possibility of metastable states.The
CPU provides only one synchronization stage to
minimize the HLDA latency. This is to avoid speed
degradations in cases of heavy HOLD activity (i.e.,
DMA controller cycles interleaved with CPU
cycles).
it is recommended to synchronize it with CTTL to
minimize the possibility of metastable states.The
CPU provides only one synchronization stage to
minimize the HLDA latency. This is to avoid speed
degradations in cases of heavy HOLD activity (i.e.,
DMA controller cycles interleaved with CPU
cycles).
INT
Interrupt.
A low level on this pin requests a maskable interrupt. INT
must be kept asserted until the interrupt is acknowledged.
A low level on this pin requests a maskable interrupt. INT
must be kept asserted until the interrupt is acknowledged.
NMI
Non-Maskable Interrupt.
A High-to-Low transition on this signal requests a non-
maskable interrupt.
Note: INT and NMI are true asynchronous inputs. There-
A High-to-Low transition on this signal requests a non-
maskable interrupt.
Note: INT and NMI are true asynchronous inputs. There-
fore, no external synchronizing circuit is needed.
CWAIT
Continuous Walt.
Causes the CPU to insert continuous wait states if
sampled low at the end of T2 and each following T-State.
Causes the CPU to insert continuous wait states if
sampled low at the end of T2 and each following T-State.
OSCIN
Crystal/External Clock Input.
Input from a crystal or an external clock source.
Input from a crystal or an external clock source.
9
ST2
8
ST3
7
PFS
6
DDIN
5
ADS
4
SPC
3
VCC
2
HBE
1
HOLDA
68
HOLD
67
RSTO
66
RES
65
RES
64
CWAIT
63
GND
62
OSCIN
61
RSTI
27
A18
28
A17
29
A16
30
VCC
31
AD15
32
AD14
33
AD13
34
AD12
35
AD11
36
AD10
37
AD9
38
AD8
39
GND
40
AD7
41
AD6
42
AD5
43
AD4
10
GN
D
11
ST
1
12
ST
0
13
IL
O
14
NMI
15
IN
T
16
U/
S
17
BPU
18
IA
S
19
IOU
T
20
VC
C
21
A23
22
A2
2
23
A21
24
A2
0
25
A19
26
GN
D
60
O
S
CO
UT
59
TS
O
58
WR
57
RD
56
GN
D
55
CTTL
1
54
VC
C
53
DB
E
52
GN
D
51
VC
C
50
CT
T
L2
49
FCL
K
48
AL
E
47
AD
0
46
AD
1
45
AD
2
44
AD
3
NS32FX164
NS32FV16
NS32FX161
68-Pin PCC Package
AR-F151
11 – 15
Click on the first or last page to see other AR-155 (serv.man13) service manuals if exist.