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The LBP block controls the laser printer engine and the FIFO memory.
Since sending/receiving of command/status with the LBP engine is
made in the serial line, serial/parallel conversion is made in this block
to make interface between the CPU and the LBP engine. The refer-
ence video signal generated in the PLL circuit is made to the video fre-
quency necessary for the dividing circuit. Video data are sent to the
laser engine in synchronization with this signal. 
A 16M DRAM (1M 

× 16 bit) is used as the printer FIFO memory, which

is used as the buffer memory in PC-scan. 

The NCU circuit has the following functions:
•

Matching between the public line and Sigma Delta circuit (MODEM
circuit)

•

To make OFF-hook state

•

Ring detection 

•

External telephone connection 

•

Detection of OFF-hook state of the external telephone

Relay RY501 connects the public line and the matching transformer.
Relay RY501 connects the DC load line and the public line.
When RY501 is open, the external telephone is connected to the public
telephone line. For calling sound from the public line, the signal is rec-
tified and inputted to the photo coupler PC817 ISO502 to generate
NCU_RDT signal. 

The CPU judges whether calling is made from the public line or not
referring to the frequency of the NCU_RDT signal. 
By turning on RY501, the public line loop is closed. Then response of
MFP is transmitted to the public line. (OFF-hook state). When the dial
pulse is selected, RY501 is turned on/off according to the telephone
number to transmit the remote telephone number to the public
telephone line. In the tone pulse, the tone signal from the Sigma Delta
circuit is passed through the matching transformer to the public
telephone line.
The NCU_LPCDT signal is generated fromPC814 (ISO503) according
to the potential generated in R513. When the external telephone is in
OFF-hook state, a potential is generated in R513 to drive the
MCU_LPCDT signal LOW. The CPU monitors the signal and judges
whether the external telephone is busy or not.

The Sigma Delta circuit converts analog signals passed through the
matching transformer into digital signals. The digital signals
(FX200_SDOUT) outputted from FX200 are inputted to the analog
switch to generate digital switch for switching with +5V/5V. The signals
are converted into analog signals in the LPF circuit.

On the other hand, the analog signals inputted through the matching
transformer are amplified in the AMP circuit. By combination with
FX_200SDBFK signal and the integrator/comparator, the FX_200SDIN
signal is made and inputted to FX200.

The data flow in each reception mode is shown below.

The FAX data from the public line are stored in the 16M DRAM. In this
case, the data are stored in the received format, that is in MH, MR or
MMR format. When reception of one page data is completed, printing
is performed. 

CLK

RST

RDYLED

CS_LBP

CA[5:0]

DATA2FPGA[15:0]

IWR_

IRD_

D_LBP2SCL[15:0]

LBP_WE_

IMG2LBP[7:0]

LBP_RDY

SCL

Module

PLL

HFKDIV

PLL_C

L

K

J[3:0]

VCLK
HS_

LBP module

ECP

module

R

ESER

R

HS
Y

N

C

_

SEL

ELDATA[5:0]

ELWR_

ELRD_

PA RERR

LEDATA[7:0]

LERDY

STALL

STSCH

DPRIM

ELDATA[7:0]

PAPPY

VSYNC

DREADY
RESET
ERROR
DDATA

DPAGE
DSRDY
DCRDY
SCLK
SDATA

RAS_
CAS_
WR_
OE
ADDR[9:0]
DATA[15:0]

DRAM
256K

x16

LBP
ENCINE

RLE

Rublic
line

External
telephone

Matching
transformer

Ring
detection

Loop
current
detection

NCU_LPCDT

NCU_RDT

Sigma Delta
circuit

To CPU

To CPU

T501

RY501

R513

ISO502

ISO503

LF347

+5V

-5V

FX200_SDOUT

HC4053(IC605)

HC4053(IC605)

LPF

LIS

FX200_CAL

LF347

FX200_GAIN

LM311

LF347

HC4053(IC516)

FX200_SDIN

FX200_SDFBK

AMP.

Integrator,Comparator

+5V

-5V

Matching

transformer

Reference voltage

FX164

FX200

NCU

Main Memory

LC8213

ASIC

Buf. Mem.

Prog.ROM

Image.

Memory

Image  Bus

CPU Bus

PSTN

Compressed
Image

(FAX reception)

Reception operation

FAX/PCL
MCU PWB

FAX/PCL
MCU PWB

LZ9FH19

SCAN
DATA
Memory

LCD PWB

AR-F151

11  – 20

The FAX data stored in the main memory are transmitted to LC8213,
where they are converted into bit map data, which are sent to ASIC
and transmitted to the FAX/PCL MCU PWB for printing.

LZ9FH19 receives image data from FAX/PCL MCU and stores in the
scan data memory.  The mage data are transmitted to LC52113 and
converted into MMR format. The converted data are stored in the main
memory then read by FX200 and transmitted to the public line.

The LCD PWB is composed of the 4-bit, single-chip microprocessor,
HD404344, the LCD panel, the key SW block, the LED circuit, and the
shunt regulator circuit. The block diagram is shown below.
The LCD PWB is composed of the key scan process block, the serial
I/O process block, the LED lighting process block, the LCD display
process block, the reset process block, the oscillation circuit, and the
LCD power circuit. These circuits are driven by 5V, and only the LCD
circuit is driven by 12V to generate 5.2V as the LCD display drive volt-
age.

Pin No.

Signal name

Input/Output

1

LED1

Output

2

LED2

Output

3

LCDRS

Input/Output

4

LCDRW

Input/Output

5

LCDB4

Input/Output

6

LCDB5

Input/Output

7

LCDB6

Input/Output

8

LCDB7

Input/Output

9

OSC1

Input

10

OSC2

Output

11

GND

–

12

KEYCOM1

Output

13

KEYCOM2

Output

14

KEYCOM3

Output

15

KEYCOM4

Output

16

V

CC

–

17

TEST

Input

18

/PANEL RESET

Input

19

/SCK

Input

20

SID

Input

21

SOD

Output

22

LCDE

Output

23

KEYCOM9

Output

24

KEYCOM8

Output

25

LED3

Output

26

KEYCOM7

Output

27

KEYCOM6

Output

28

KEYCOM5

Output

FX164

FX200

NCU

Main Memory

LC8213

ASIC

Buf. Mem.

Prog.ROM

Image.

Memory

CPU Bus

PSTN

Compressed
Image

Image Bus

(FAX reception)

Print operation

FAX/PCL
MCU PWB

LZ9FH19

FAX/PCL
MCU PWB

SCAN
DATA
Memory

LCD PWB

FX164

FX200

NCU

Main Memory

ASIC

Buf. Mem.

Prog.ROM

Image.

Memory

CPU Bus

PSTN

Compressed
Image

Image Bus

LC8213

(FAX transmission)

FAX/PCL
MCU PWB

FAX/PCL
MCU PWB

LZ9FH19

SCAN
DATA
Memory

LCD PWB

Key scan section

LED circuit section

LCD power circuit

LCD panel

Oscillation 
circuit

FAX board
PWB

LCD PWB

CPU
HD404344

SOD

SCK
SIO
RESET

AR-F151

11  – 21

Pin No.

Signal name

Input/Output

Remark

1

LCDRS

Input

H: Data input;
L: Instruction input

2

LCDRW

Input

H: Data read;
L: Data write

3

LCDE

Input

Enable signal

4

DB0

Input

Not used.

5

DB1

Input

Not used

6

DB2

Input

Not used

7

DB3

Input

Not used

8

LCDB4

Input

Data bus line

9

LCDB5

Input

Data bus line

10

LCDB6

Input

Data bus line

11

LCDB7

Input

Data bus line

12

V

SS

–

0V

13

V

DD

–

+5.2V

14

Vin

–

+5.2V

15

V5

–

LCD drive power

16

GND

–

Frame GND

LCD display data
process time (B)

Key scan
process
time (A)

Key scan
process
time (A)

Key SW effective period 

input

AR-F151

11  – 22

Pin No.

Signal name

Input/Output

Remark

1

LCDRS

Input

H: Data input;
L: Instruction input

2

LCDRW

Input

H: Data read;
L: Data write

3

LCDE

Input

Enable signal

4

DB0

Input

Not used.

5

DB1

Input

Not used

6

DB2

Input

Not used

7

DB3

Input

Not used

8

LCDB4

Input

Data bus line

9

LCDB5

Input

Data bus line

10

LCDB6

Input

Data bus line

11

LCDB7

Input

Data bus line

12

V

SS

–

0V

13

V

DD

–

+5.2V

14

Vin

–

+5.2V

15

V5

–

LCD drive power

16

GND

–

Frame GND

LCD display data
process time (B)

Key scan
process
time (A)

Key scan
process
time (A)

Key SW effective period 

input

AR-F151

11  – 22