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AR-155 (serv.man13)
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Service Manual
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Copying Equipment / AR150 155 ARF151 Service Manual-Electrical Section
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Output Signals
A16 
∼ A23 ∗ High-Order Address Bits.
These are the most significant 8 bits of the memory ad-
dress bus.
HBE
∗ High Byte Enable.
Status signal used to enable data transfers on the most
significant byte of the data bus.
ST0 
∼ 3
Status.
Not used.
U/S
User/Supervisor.
Not used.
ILO
Interlocked Operation.
Not used.
HLDA
Hold Acknowledge.
Activated by the CPU in response to the HOLD input to in-
dicate CPU has released the bus.
PFS
Program Flow Status.
A pulse on this signal indicates the beginning of execution
of instruction.
BPU
BPU Cycle.
Not used.
RSTO
Reset Output.
This signal becomes active when RSTI is low, initiating a
system reset.
RD
Read Strobe.
Activated during CPU or DMA read cycles to enable read-
ing of data from memory or peripherals.
WR
Write Strobe.
Activated during CPU or DMA write cycles to enable writ-
ing of data to memory or peripherals.
TSO
Timing State Output.
Not used.
DBE
Data Buffers Enable.
Used to control external data buffers. It is active when the
data buffers are to be enabled.
OSCOUT
Crystal Output.
Not used.
IAS
SPecial Cycle Address Strobe.
Not used.
CTTL1  – 2 System Clock.
Output clock for bus timing. CTTL1 and CTTL2 must be
externally connected together.
FCLK
Fast Clock.
Not used.
ALE
Address Latch Enable.
Active high signal that can be used to control external ad-
dress latches.
IOUT
Interrupt Output
Not used.
Input-Output Signals
AD0 
∼ 15
* Address/Data Bus.
Multiplexed Address/Data Information. Bit 0 is the least
significant bit of each.
SPC
Slave Processor Control.
Not used.
DDIN
* Data Direction.
Status signal indicating the direction of the data transfer
during a bus cycle. During HOLD acknowledge this signal
becomes an input and determines the activation of RD or
WR.
ADS
* Address Strobe
Controls address latches; signals the beginning of a bus
cycle. During HOLD acknowledge this signal becomes an
input and the CPU monitors it to detect the beginning of
a DMA cycle and generate the relevant strobe signals.
When a DMA is used, ADS should be pulled up to V
CC
through a 10 k
Ω resistor.
(3) LC8213K (IC505) Pin Layout
I:
Input pin
O:
Output pin
B:
Bidirectional pin
P:
Power pin
NC: Not connected
No.
Pin name
Type
1
CS
I
2
RD
I
3
WR
I
4
A2
I
5
A1
I
6
A0
I
7
V
DD
P
8
NC
9
D7
B
10
D6
B
11
D5
B
12
D4
B
13
V
SS
P
14
D3
B
15
D2
B
16
D1
B
17
D0
B
18
NC
19
NC
20
IREQ
O
21
DREQ
O
22
DACK
I
23
NC
24
NC
25
NC
26
NC
27
RESET
I
28
CLK
I
29
V
SS
P
30
TEST4
I
31
V
DD
P
32
TEST3
I
33
TEST2
I
34
TEST1
I
35
TEST0
I
36
NC
37
BREQ
O
38
BACK
I
39
IDREQ
I
40
IDACK
O
No.
Pin name
Type
41
AEN
O
42
AST
O
43
MDEN
O
44
MRD
O
45
MWR
O
46
IORD
O
47
IOWR
O
48
LDE
O
49
UDE
O
50
READY
I
51
DTC
O
52
V
SS
P
53
NC
54
MA23
O
55
MA22
O
56
MA21
O
57
MA20
O
58
MA19
O
59
MA18
O
60
MA17
O
61
MA16
O
62
MA/MD15
O
63
V
SS
P
64
MA/MD14
B
65
MA/MD13
B
66
MA/MD12
B
67
MA/MD11
B
68
MA/MD10
B
69
MA/MD9
B
70
MA/MD8
B
71
MA/MD7
B
72
V
SS
P
73
V
DD
P
74
MA/MD6
B
75
MA/MD5
B
76
MA/MD4
B
77
MA/MD3
B
78
MA/MD2
B
79
MA/MD1
B
80
MA/MD0
B
AR-F151
11  – 16
(4) CPU interface
Terminal
name
Pin
No.
I/O
Function
CS
1
I
Chip select for the CPU to access
the LC8213 (low sctive).
RD
2
I
Read.Set to “L” when the CPU is
the read out the LC8213 register.
WR
3
I
Write.Set to “L” when the CPU is
to the LC8213 register.
A2
4
I
Address input for when the CPU
accesses LC8213.
A1
5
A0
6
D7
9
I/O
3 state
Bidirectional 8-bit data bus
D6
10
D5
11
D4
12
D3
14
D2
15
D1
16
D0
17
IREQ
20
O
Interrupt request signal for the
CPU. By reading out the INTR
(interrupt request register) the CPU
can find the cause of the
interruption.IREQ is set to “L” when
the CPU reads INTR.
DREQ
21
O
DMA request signal for the external
DMA controller. This will be set to
“H” in the following cases. 
• Data exists in the EFIFO during
the coding processes.
• An empty space exists in the
DFIFO during decoding processes.
• The DBUF can read/write during
data transfer between the image
memory bus and CPU bus.
DACK
22
I
DMA acknowledge signal from the
external DMA comtroller.If DACK is
set to “L” during coding or
decoding, EFIFO and DFIFO will
be accessed. DBUF will be
accessed if DACK is set to “L”
during data transfer between the
image memory bus and CPU bus.
(5) Image memory interface
Terminal
name
Pin 
No.
I/O
Function
MA23
54
O
3 state
Not used.
MA22
55
MA21
56
MA20
57
MA19
56
MA18
59
MA17
60
MA16
61
MA/MD15
62
I/O
3 state
Not used.
MA/MD14
64
Low-order 16-bit address and 16-
bit data bus for the image memory.
MA/MD13
65
MA/MD12
66
MA/MD11
67
MA/MD10
68
MA/MD9
69
MA/MD8
70
Terminal
name
Pin 
No.
I/O
Function
MA/MD7
71
MA/MD6
74
MA/MD5
75
MA/MD4
76
MA/MD3
77
MA/MD2
78
MA/MD1
79
MA/MD0
80
AEN
41
O
This is set to “L” when the
LC8213 is the bus master to the
image memory.
If AEN = “H”, MA/MD, MRD,
MWR,  IORD,  IOWR,  UDE and
LDE will be a HiZ output.
AST
42
O
This signal indicates that an
address is being output to
MA/MD15  
∼   MA/MD0.
MDEN
43
O
This signal indicates that the
LC8213 is using MA/MD15  
∼ 
MD0 as  data buses.
USE
49
I/O
3 state
Not used.
LDE
48
I/O
3 state
This signal indicates that the low-
order bits of the data bus are
being used.
MRD
44
O
3 state
This is set to “L” when data is
being read out of the image
memory.
MWR
45
O
3 state
This is set to “L” when data is
being written into the image
memory.
IORD
46
O
3 state
Not used.
IOWR
47
O
3 state
Not used.
BREQ
37
O
This signal is used for the LC8213
to request usage rights from the
image memory bus.
BACK
38
I
Input signal allowing the LC8213
to use the image memory bus.
IDREQ
39
I
Not used.
IDACK
40
O
Not used.
READY
50
I
This signal is used to delay the
read/write signal when using low
speed image memory or an I/O
device.
DTC
51
O
Not used.
(6) Others
Terminal
name
Pin No.
I/O
Function
CKL
28
I
External clock (Max.20NHz)
RESET
27
I
Reset
TEST0
35
I
For testing.This is normally fixed
to  “L”.
TEST1
34
TEST2
33
TEST3
32
TEST4
30
V
DD
7, 31,
73
power supply (+ 5V)
V
SS
13, 29,
52, 63,
72
GND
AR-F151
11  – 17
(7) MBCG46533-175 (IC 509) Pin Loyout
Pin#
Signal
Description
1:18
IA14:IA0
Image bus address
19
AI_LINEINT
Scanner line interuppt to
FX200 INT1 pin
20
CEP_*LED
Chip select to image memory
21
AI_TRIG
Tigger signal to LC82103
22
AI_*IPDACK
DMA ack. sugnal to LC82103
23
IM_*WR
Write strobe to image
memory
24
AI_CEP*DREQ
DMA request to FX200
25
AI_BACK
Bus ack.signal to LC8213
28
IP_CLK1
CLK1 of the LC82103
32
AI_*CEPDMAK
DMA ack.signal from FX200
33
IM_IPDREQ
DMA request from LC82103
34: 42
IDATA7: IDATA0
Image bus data
44
IM_IPSH
SH signal from LC82103
45
IM_BREQ
Bus request from LC8213
46
CEP_DREQ
DMA request from LC8213
47
CEP_*AEN
Address enable signal from
LC8213
48
CEP_AST
Address strobe signal from
LC8213
49
*RESET
Reset signal from LBP
engine
51
VCKL
Not used
53
*DREADY
DREADY signal from LBP
54
ERROR
ERROR signal from LBP
55
*DCRDY
DCRDY signal from LBP
56
*HSYNC
Horizontal syc.signal from
LBP
57
*SCLK
SCLK signal from LBP
58
VSYNC
Vertical signal from LBP
59
PLL-CLK
Basic clock from PLL
62
*DDATA
Video data to LBP
63
*DSRDY
DSRDY signal from LBP
64
*SDATA
SDATA for LBP
65
RES-*ERR
RESERR to LBP
66
*DPAGE
DPAGE to LBP
67
*DPRIM
DPRIM to LBP
69
AI-*MWE
Write strobe to 16MDRAM
70
AI-*ICAS
L-CAS signal to 16MDRAM
71
AI-*UCAS
U-CAS signal to 16MDRAM
73
*ICAS
CAS signal from FX200
74
*IWEI
Write enable signal for even
byte on data bus
75
*IWE0
Write enable signal for odd
byte on data bus
76
FX1_*RSTO
Reset signal from FX164
77
AI_*IRD
read strobe to I/O device
78
AI_*IWR
write strobe to I/O device
80
AI_*SANWRL
Strobe signal for LD0:8 bus
81:89
LD0:LD7
Buffered AD bus for slow
devices access
90
AI_*CSIP
Chip select signal for
LC82103
91
AI_*CSCEP
Chip select signal for LC8213
92
AI_*RDKRB
Read strobe signal for
74LS244
93
AI_*FIFOA9
WPSFIFO address signal
Pin#
Signal
Description
94
AI_*CSCONF
Chip select signal for
64KSRAM
95
AI_*WRLED
Not used
98
F2_*SEL1
Zone select signal from
FX200,
99
F2_*SEL3
Zone select signal from
FX200
100
F2_*DMAK0
DMA ask.signal from FX200
101
F1_*DBE
Data buffer enable signal
from FX164
102
F1_*DDIN
Status signal indicating the
direction of the data bus
from FX164
103
F1_*RD
Read strobe signal from
FX164
104
F1_*WR
Write strobe signal from
FX164
108
F1_CTTL1
System clock from FX164
110
F1_*HLDA
Hold Ask. signal from FX164
111
F1_ALE
Address latch signal from
FX164
112:129
AD15:AD0
FX164 AD bus
132
*XINT
1284 INT signal
133
XSELECT
1284 SELECT signal
134
XPERR
1284 PERR signal
135
XBUSY
1284 Busy signal
136
XACK
1284 ACK signal
137
XFAULT
1284 FAUL signal
138:146
BPCDATA1:BPCDATA8
1284 buffered data
148
*XSTROBE
1284 STROBE signal
149
*XSLECTION
1284 SELECT IN signal
150
*XAUTOFD
1284 AUTOFD signal
151
AI_1284IN
1284 buffer direction control
signal
152
AI_ECPINT
1284 interrupt signal to
FX200
153
AI_*DREQ
155
XTST
TEST pin
156
SW4M
FIFO RAM size select signal
157:174
AI_FIFOD0:
AI_FIFOD15
WIPS FIFO Data
175
AI_FIFO*WR
WPS FIFO write strobe
177
AI_FIFO*CAS
WPS FIFO CAS signal
178
AI_FIFO*RAS
WPS FIFO RAS signal
179:188
AI_FIFOA0:AI_FIFOA8
WPS FIFO address signal
190:193
AI_SMPH0:AI_SMPH3
Scanner motor phase signal
194:195
AI_CUR0:AI_CUR1
Scanner motor current
control signal
197
AI_*CLK2
CLK2 signal for CCD
198
AI_*CLK1
CLK1 signal for CCD
199
AI_*CLAMP
CLAMP signal for CCD
202
AI_*LAMPON
Scanner lamp control signal
203
AI_*TGCCD
TG signal for CCD
204
AI_*RSCCD
RS signal for CCD
205
PNL_*SCOVER
Scanner cover open signal
206
*B4SEN
B4 sensor signal (Not used
in not-Japan model)
207
*PISEN
Paper in Sensor on Scanner
signal
208
*ORSEN
Original sensor on scanner
signal
AR-F151
11  – 18
5. FAX PWB circuit description (AR-F151
only)
(1) Summary
The FAX PWB performs the following operations:
•
Interface with the MCU PWB (Scan data input, print image data out-
put)
•
FAX operation panel control
•
FAX image conversion
•
Interface with the public telephone line
NS FX164 is used as the CPU, and FX200 is used as the system con-
troller. An 8M OTPROM is used as the program ROM, and16M DRAM
as the main memory. To store the registered telephone numbers, etc.,
64K SRAM (backed up by battery) and the clock IC are used.
LC8213 is used to perform data compression and expansion.
ASIC performs laser printer control and interface with and the MCU
PWB.
The NCU circuit connects with the telephone line.
(2) CPU section
The NS32FX164 (having 32bit core and 16bit DSP core) is used as the
CPU in combination with the system controller NS32FX200. The 32bit
CPU core is used to control the system. By combination with the 16bit
DSP core and the Sigma Delta Coded circuit in the NS32FX200, the
MODEM function is realized. The NS32FX200 is provided with the
DRAM controller function, the interrupt controller function, the timer
function, and the DMA controller function, which are used to control the
system.
(3) Memory
A DRAM of 16M (1M 
× 16 bit composition) is used as the main
memory. An 8M OPTROM (512K 
× 16 bit composition) is used as the
program memory. 
The NJU6355 is used as the clock IC, and 64K SRAM of 8K 
× 8bit is
used as the configuration memory which stores various settings. These
two IC’s are backed up by a 3V lithium battery even when the AC
power is turned off. The configuration memory is also used as the buff-
er memory in PC-FAX.
(4) Scanner image storing process
ASIC (LZ9FH19) receives scanner image data processed in the MCU
PWB and stores in the scan data memory.
ASIC outputs image data to the image data bus and performs com-
pression and expansion with LC8213 according to the CPU’s instruc-
tion.
(5) Compression, expansion
By combination of LC8213 and 256K SRAM, compression and expan-
sion are performed. 
This IC converts bit map data into coded data in MH, MR, or MMR for-
mat or converts coded data of MH, MR, or MMR format into bit map
data. In FAX sending, bit map data is outputted from LZ9FH19 to the
image bus are coded in MMR format and outputted to the CPU bus.
The coded data are stored in the main memory. In FAX reception, the
coded data are read from the main memory and converted into bit map
data by this IC and outputted to the image bus.
The outputted data are sent through the ASIC to the MCU PWB and
printed. The 256K SRAM connected to the image bus are used as the
buffer memory.
(6) ASIC section 
This ASIC of about 30,000 gates is composed of the three blocks.
•
SCL block: Scanner control and bus control
•
1284 block: Interface section with PC
•
LBP: Laser printer engine control and FIFO memory control
RESET_GEN forms reset signals in ASIC, and CLOCK GEN forms
clock signals in ASIC. HFKDIV divides the basic video frequency in-
putted to the ASIC.
SCL block 
The SCL block performs scanner control, timing control, and bus con-
trol.
The scanner control block does not use the MCU because the MCU
takes an image data.
The sensor block receives input of the sensor and switch state on the
ADF. The bus control block performs the CPU bus control, image bus
control, and DMA transmission between them. The timing control block
forms CCD clock signals and DMA signals.
CPU NS32FX164
32bit CPU CORE
16bit DSP module
System controller NS32FX200
DRAM controller
Interrupt controller
Timer
DMA controller
Sigma Delta Coded
Analog 
circuit
NCU 
circuit
Public Telephone line
CPU 
Bus
CPU 
Interface
Compression
Expansion
Image Bus 
Interface
LC8213
Image Bus
256K 
SRAM
LBP
ECP
SCL
Reset_gen
ASIC
Hfckdiv
Clock gen
Scanner control
Motor control
Lamp modulation
Bus control
DMA control
CAPTURE
Image bus
control
Timing control
Sensors
TC
Ti
m
e
 s
lo
t
CCd timing 
conrol
LC8213 Dreq out
ECP Dreq out
C
T
T
L
 di
v2
 m
a
in
 c
loc
k
C
T
TL
 fr
o
m
 FX
LC
8210
3 C
C
D
 t
im
ing
LC
8
2
1
3
 Dr
eq i
n
EC
P D
re
q
 in
L
C
8
2
1
0
3 D
M
A
 han
ds
hak
e
L
C
8
2
1
3
 BR
EQ
LC8
213 B
A
CK
LC8
213 c
o
nt
ro
s
Im
age m
e
m
o
ry
 addr
e
ss
Im
a
g
e
 m
e
m
o
ry
 d
a
ta
 b
u
s
Im
a
g
e
 m
e
mo
ry co
n
tr
o
l
Address
FX data in
FX data out
Controls
LBP READY
LBP 
DACK/wrne
Data tp LBP
Con
tr
o
l
FX
 A
D
 B
U
S
Control
Address
FX 
data in
FX 
data 
out
F
X
 dat
a
 out
Co
n
tro
l
Im
a
g
e a
d
dr
e
s
s
Im
a
g
e
 me
mo
ry
 co
n
tro
l
LC
8213
 DA
T
A
DA
CK
DR
E
Q
Im
age 
dat
a
 on
Im
a
g
e
 
wr
n
e
Ca
p
tu
r 
on
AR-F151
11  – 19
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