Sharp ER-A770 (serv.man4) Service Manual ▷ View online
10. WAIT control
The weight control function built in the MPCA8 is used to provide an
interface with low-speed devices.
interface with low-speed devices.
10-1. Block diagram
The block diagram of the wait control function is shown.
In the figure, the decoder, wait enabling register, AND-OR sections
are the same as those in the MPCA6 or 7, but other components are
newly incorporated in the MPCA7.
are the same as those in the MPCA6 or 7, but other components are
newly incorporated in the MPCA7.
EXWAITZ and WAITZ are external weight signals which are to be
ORed inside the MPCA8 and output to the WAITZ. The EXWAITZ is a
general-purpose wait request terminal, and WAITZ is the wait request
signal from the VGA controller.
ORed inside the MPCA8 and output to the WAITZ. The EXWAITZ is a
general-purpose wait request terminal, and WAITZ is the wait request
signal from the VGA controller.
11. CKDC9
The ER-A770 on CKDC9 for the CKDC PWB and one CKDC9 for
POLE display (option) to carry out the following control operations.
POLE display (option) to carry out the following control operations.
CKDC PWB CKDC9:
Clock (second data readable)
Buzzer
System reset
Key/Clerk switch
POLE CKDC9(UP-P16DP or UP-I16DP)
Customer display tube
11-1. Interface
CKDC9 is connected through the MPCA8.
12. Option RAM interface
12-1. Interface
The expanded RAM connector terminals are shown in the table.
The 72 pin S.O. DIMM is used for the connector.
Extension RAM connector terminals
Selector
/AS
CLK WAIT RESET Counter
START
/RESET
/EXWAIT
/VWAIT
/LCDWAIT
/WAITZ
φ
WAIT
enable
For
RASP-
/RESET for 1,2,3WAIT
WAIT
enable
For
MISC
WAIT
Count
For
RASP
D
/Q
Selector
Selector
/RESET
/RESET
for
1WAIT
for
1WAIT
/RESET
WAIT
Count
For
MISC
WAIT
Count
For
RASPN
WAIT
Count
For
RASPN
D
/Q
D
/Q
WAIT
enable
For
VRAM
•
VGA
I/O
D
/Q
Terminal autoweight signal
Fig. 10
TXD2(P87)
SCK2(P83)
SCK2(P83)
RXD2(P84)
TXDI
SCKI
SCKI
RXDI
H8/510
MPCA8
INT1
IRQ0
IRQ0
RES
STOP
(P57)
RESET
RESET
STH
HTS
SCK
SCK
CKDC9
KRQ
SHEN
SHEN
STOP
HTS2
SCK2
STH2
SCK2
STH2
HTS
SCK
STH
SCK
STH
SRES
RESET
SW
FTI2
CKDC9
HTS1
SCK1
STH1
SCK1
STH1
HTS
SCK
STH
SCK
STH
INT4
SHEN
RESET
reset from MAIN
VFDC
VFD
UP-P16DP/UP-I16DP
Key
Buzzer
Signal
Name
Pin
No.
GND
1
GND
2
—
3
—
4
—
5
—
6
—
7
—
8
—
9
—
10
A14
11
A15
12
A16
13
A17
14
A18
15
A19
16
—
17
PCE22_E
18
PCE21_E
19
—
20
PSREF
21
PCE22_O
22
PCE21_O
23
GND
24
Signal
Name
Pin
No.
—
25
—
26
—
27
—
28
A13
29
A12
30
A11
31
A10
32
A9
33
A8
34
A7
35
A6
36
A5
37
A4
38
A3
39
A2
40
A1
41
A0
42
D15
43
D14
44
D13
45
D12
46
D11
47
D10
48
Signal
Name
Pin
No.
D9
49
D8
50
D7
51
D6
52
D5
53
D4
54
D3
55
D2
56
D1
57
D0
58
GND
59
NC
60
OWR
61
—
62
—
63
—
64
—
65
—
66
HWR
67
—
68
VMEM
69
VMEM
70
GND
71
GND
72
13. Reset sequence
The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
13-1. Power ON/OFF
The flow of signal processing at the time of the power supply turning
On/Off is as follows:
On/Off is as follows:
Table 19
<Power OFF>
Power supply
MPCA8
CPU
CKDC9
1
POFF
L
2
IRQ0
L
3
STOP
L
4
RESET
L
(System reset)
Table 20
<Power ON>
Power supply
MPCA8
CPU
CKDC9
1
POFF
H
2
RESET
H
(System reset)
The table below shows the timing chart.
13-2. MRS, SRV reset
The ER-A770 does not have the mode switch. The procedure for
resetting MRS, SRV is different from that of conventional cash regis-
ters.
in the ER-A770, MRS, SRV resetting is selected and executed by the
key which has bee depressed when the CKDC reset is released to
start the system.
resetting MRS, SRV is different from that of conventional cash regis-
ters.
in the ER-A770, MRS, SRV resetting is selected and executed by the
key which has bee depressed when the CKDC reset is released to
start the system.
(In the case of MRS, security is added by a key operation equivalent
to a pass word.)
to a pass word.)
Flow chart
14. Drawer
The ER-A770 can use up to 2 optional external drawers.
14-1. Drawer solenoid drive
P34 P37 inside the CPU are allocated for the port output of the
drawer solenoid drive.
drawer solenoid drive.
Built-in port
Signal name
Remarks
P34
DR0
Drawer 1 (optional drawer)
P35
DR1
Drawer 2 (optional drawer)
P36
DR2
Reserved
P37
DR3
Reserved
One port corresponds to one drawer. Theoretically, it is possible to
drive multiple drawers at the same time, but this processing must be
inhibited softwarewisely because of power supply capacity and driver
hardware factors. If a power failure is detected, the drawer solenoid
drive must be stopped as soon as possible.
drive multiple drawers at the same time, but this processing must be
inhibited softwarewisely because of power supply capacity and driver
hardware factors. If a power failure is detected, the drawer solenoid
drive must be stopped as soon as possible.
The drawer solenoid drive time must controlled in the range of 40
ms to 50 ms by the timer.
ms to 50 ms by the timer.
14-2. Drawer open/close sense
The drawer open/close sense signal is input into the built-in port of
the CPU. the sense signal of an optional drawer sensor is also wired
ORed before inputting.
the CPU. the sense signal of an optional drawer sensor is also wired
ORed before inputting.
P33=1: Any of the drawers is open.
POFF
CKDCR
(CKDC reset)
VCC
POFF
INT0
IRQ0
STOP
RESET
(System reset)
SLIDE
SW
SW
CKDC9
MPCA8
POWER
SUPPLY
SUPPLY
CPU
Fig. 14
PG GOOD
RESET
STOP
SHEN
SCK
+5V,+12V
(POFF)
10ms MIN
8 PULSE
(System)
Power supply On
Power supply Off
Fig. 15
Yes
No
*Slide Switch
operation
operation
MRS1 key
ON?
MRS2 key
ON?
CKDC start
SRV reset
MRS reset
Star
t
Normal
start?
condition read
Recovery
No
Yes
OK?
OK?
SRV reset
SRV reset
No
Yes
Yes
No
Yes
Yes
No
Hard reset
start?
PASSWORD
judgement
judgement
judgement
10-key position
input sequence
input sequence
MRS reset
PASSWORD
Fig. 16
15. SRN
The SRN of the ER-A770 is compatible with the ER-A750.
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the ER-A770 cannot use the IRQ1 terminal
instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5 and 6 for the ER-A7RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the ER-A770 cannot use the IRQ1 terminal
instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5 and 6 for the ER-A7RS.
17. MCR
This paragraph describes MCR option (UP-E12MR) control defined
by ER-A770 hardware architecture.
2 channels of the serial port (interchangeable with 8251) built in the
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E12MR)
by ER-A770 hardware architecture.
2 channels of the serial port (interchangeable with 8251) built in the
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E12MR)
17-1. CPU interface
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the ER-A770 system is shown below.
(MCM-21) in the ER-A770 system is shown below.
Signal description
RCP1
TRACK 1 CLOCK PULSE
RDD1
TRACK 1 DATA SIGNAL
RCP2
TRACK 2 CLOCK PULSE
RDD2
TRACK 2 DATA SIGNAL
CLS1
TRACK 1 CARD DETECTION SIGNAL
CLS2
TRACK 2 CARD DETECTION SIGNAL
RCVRDY1
TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2
TRACK 2 DATA RECEIVING SIGNAL
INTMCR
INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
RCVRDY and SYNC input
2 chip select signals for 8251 are generated inside MPCA8.
17-2. MCR interface
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
18. 1-HOLE CLERK
On the ER-A770, 1-hole clerk key with up to 8 bits can be used.
The 1-hole clerk switch is controlled through the CKDC9 on the main
board.
board.
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8
in the ER-A770 system.
in the ER-A770 system.
RCVCLK1
/DSR2
RCVRDY2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
"0" "1" "1"
Approx. 16µ s
Min. 5 µ s
RDD1/RDD2
RCP1/RCP2
CKDC9
ST0 ST3
LS138
X2
/S2 /S9
/CFSR
8
7
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
CPU
10
0p
FX4
/A
S
/R
D
/R
F
S
H
#
/H
W
R
/L
W
R
IP
L
O
N
0
VCC
V
CC
VCC
V
CC
VCC
VCC
VCC
NOT USED
NOT USED
X4
19
.6
6M
H
z
R1
79
47
R1
73
4
7
R1
65
4
7
R1
57
4
7
R1
51
4
7
R1
38
4
7
C1
77
C1
59
C1
68
C1
70
C1
72
C1
74
R1
78
10
K
R1
37
10
K
R1
50
10
K
R1
56
10
K
R1
64
10
K
R1
72
10
K
RES
1
NMI
2
VSS
3
D0
4
D1
5
D2
6
D3
7
D4
8
D5
9
D6
10
D7
11
D8
12
D9
13
D1
0
14
D1
1
15
D1
2
16
D1
3
17
D1
4
18
D1
5
19
VSS
20
A0
21
A1
22
A2
23
A3
24
A4
25
A5
26
A6
27
A7
28
A8
29
A9
30
A10
31
A11
32
A12
33
A13
34
A14
35
A15
36
VSS
37
A16
38
A17
39
A18
40
A19
41
A20
42
A21
43
A22
44
A23
45
VSS
46
P30 W
A
IT
47
P31 BA
CK
48
P32 BRE
Q
49
P33
50
P34
51
P35
52
P36
53
P37
54
VCC
55
P40
56
P41
57
P42
58
P43
59
FT
I1 P44
60
P45
61
FT
I2 P46
62
P47
63
VSS
64
P50
65
P51
66
P52
67
P53
68
P54
69
P55
70
P56
71
P57
72
P60
73
P61
74
P62
75
P63
76
P64
77
P65
78
P66
79
P67
80
VSS
81
AVSS
82
P70
83
P71
84
P72
85
P73
86
AVCC
87
VCC
88
IR
Q
0
89
IR
Q
1
90
SCK1 I
R
Q2
91
SCK2 I
R
Q3
92
RXD1
93
TXD1
94
RXD2
95
TXD2
96
VSS
97
EXT
AL
98
XTA
L
99
VSS
10
0
X
10
1
E
10
2
AS
10
3
RD
10
4
HWR
10
5
LW
R
10
6
RFSH
10
7
VCC
10
8
MD0
10
9
MD1
11
0
MD2
11
1
STB
Y
11
2
IC
3
0
HD6
41
51
08
10
/R
ES
ET
NMI
VCC
R1
74
C2
30
D
[0
..1
5]
D0
D1
D2
D3
D4
D5
D6
D7
VCC
R2
14
R2
19
R2
25
R2
26
R2
20
R2
15
R2
11
10
K
X
8
R2
31
R2
21
C2
22
C2
38
C2
49
C2
39
C2
31
C2
23
C2
15
10
0p
F
X8
A
[0
..2
3]
D
[0
..1
5]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
A5
A6
A7
A8
D8
D9
D1
0
D1
1
D1
2
D1
3
D1
4
D1
5
VCC
R2
27
R2
32
R2
35
R2
33
R2
28
R2
22
R2
17
10
K
X
8
R1
80
R2
16
R2
10
R2
12
R2
05
R2
06
R1
98
R2
00
R1
95
R2
01
C2
32
C2
40
C2
50
C2
51
C2
59
C2
41
C2
33
C2
25
10
0p
F
X8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0
D1
1
D1
2
D1
3
D1
4
D1
5
R1
58
R1
46
R1
44
R1
53
R1
67
R1
54
R1
68
R1
66
R1
52
R1
43
R1
47
R1
59
R1
75
R1
60
R1
76
10
0
X
1
6
SCKI
RXDI
TXDI
/I
R
Q
0
/I
R
Q
1
FVP
O
N
NORDY
BANK
/IPLON1
VCC
VCC
V
CC
VCC
2
1
X7
19
.6
60
8M
H
z
TXD2
NOT USED
RCVDT2
!
B
e
S
hor
t P
a
tte
rn
UASCK
FROM
M
P
CA
8
R1
33
10
K
R1
39
10
K
SW
3
IP
L
O
N
S
W
R1
32
10
K
R1
31
3
3
C1
7
10
uF
/10
V
O
S
C1
47
0.1u
F
FB1
5
BF
W
7
55
0R2
X1
1
X2
2
GND
3
FS0
4
OE#
8
FS1
7
VDD
6
CL
K
5
IC
2
7
W42
C
31
-0
3
R1
30
0
R1
36
VCC
FOR
RS2
3
2
C
CH8
C1
46
8p
F
C1
45
8p
F
C3
0
10
uF
/10
V
O
S
/S
T
O
P
MCRI
NT
/I
P
L
O
N
0
/S
HE
N1
/IPLON0
VCC
VCC
VCC
/C
I2
/R
T
S
2
/DCD2
/C
T
S
2
/D
S
R
2
/D
T
R
2
FOR
RS2
3
2
C
CH8
C1
51
0.1u
F
C1
63
33
0p
F
R1
48
10
K
C1
34
47
0p
F
R1
40
10
K
C1
54
33
0p
F
/B
A
C
K
/B
R
E
Q
DOPS
/DR0
/DR1
/W
A
IT
VCC
C2
17
C2
09
C1
95
C1
96
C1
89
10
0p
F
X8
C1
88
C1
91
C1
92
C1
85
C2
58
C2
48
C1
13
C1
08
10
0p
F
X8
R1
41
10
K
C1
83
0.
1u
F
A18
A19
A20
A21
A22
A23
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
R1
99
R2
13
R2
07
R1
96
R1
97
R1
88
R1
86
R1
89
R1
90
R1
87
R2
30
R2
34
R7
8
R7
7
10
K
X
2
4
C1
80
C2
24
C2
14
C2
16
C2
07
C2
08
C2
01
C2
02
10
0p
F
X8
C1
93
C2
03
C1
94
C1
55
10
0p
F
C1
65
10
0p
F
1/14
CHAPTER 8. CIRCUIT DIAGRAM
1. Main PWB
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