Sharp ER-A770 (serv.man4) Service Manual ▷ View online
3) General description
The CPUs are fourth-generation enhanced microprocessors with ex-
ceptional computational power. They offer higher system throughput
and more efficient memory utilization than comparable second- and
third-generation microprocessors. Theinternal registers contain 208
bits of read/write memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers
which may be used individually as either 8-bit registers or as 16-bit
register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes either set of
main or alternate registers accessible to the programmer. The alter-
nate set allows operation inforeground-background mode or it may be
reserved for very fast interrupt response.
The CPU also contains a Stack Pointer, Program Counter, two index
registers, a Refresh register (counter), and an Interrupt register. The
CPU is easy to incorporate into a system since it requires only a
single +5V power source. All output signals are fully decoded and
timed to control standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary functions of
the processors. Subsequent text provides more detail on the I/O con-
troller family, registers, instruction set, interrupts and daisy chaining,
and CPU timing.
ceptional computational power. They offer higher system throughput
and more efficient memory utilization than comparable second- and
third-generation microprocessors. Theinternal registers contain 208
bits of read/write memory that are accessible to the programmer.
These registers include two sets of six general-purpose registers
which may be used individually as either 8-bit registers or as 16-bit
register pairs. In addition, there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes either set of
main or alternate registers accessible to the programmer. The alter-
nate set allows operation inforeground-background mode or it may be
reserved for very fast interrupt response.
The CPU also contains a Stack Pointer, Program Counter, two index
registers, a Refresh register (counter), and an Interrupt register. The
CPU is easy to incorporate into a system since it requires only a
single +5V power source. All output signals are fully decoded and
timed to control standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary functions of
the processors. Subsequent text provides more detail on the I/O con-
troller family, registers, instruction set, interrupts and daisy chaining,
and CPU timing.
4) Pin description
Pin
No.
Symbol
Signal
name
In/Out
Function
1
CLK
CLK
In
Clock
2
D4
S D4
In/Out
Data bus
3
D3
S D3
In/Out
Data bus
4
D5
S D5
In/Out
Data bus
5
D6
S D6
In/Out
Data bus
6
+5V
VCC
—
+5V
7
D2
S D2
In/Out
Data bus
8
D7
S D7
In/Out
Data bus
9
D0
S D0
In/Out
Data bus
10
D1
S D1
In/Out
Data bus
11
NC
NC
—
NC
12
INT
S INT
In
Interrupt request signal
13
NMI
VCC
—
Non-maskable interrupt
signal
signal
14
HALT
VCC
—
+5V
15
MREQ
S MRQ
Out
Memory request signal
16
IORQ
S IORQ
Out
Input / Output request signal
17
NC
NC
—
NC
Pin
No.
Symbol
Signal
name
In/Out
Function
18
RD
S RDS
Out
Rread signal
19
WR
S WRS
Out
Write signal
20
BUSAK
BUSAK
Out
Bus acknowledge signal
21
WAIT
S WAIT
In
Wait signal
22
BUSRQ
BUSRQ
In
Bus request signal
23
RESET
S RES
In
Reset signal
24
M1
S M1
Out
Machine cycle one signal
25
RFSH
NC
—
NC
26
GND
GND
—
GND
27
A0
S A0
Out
Address bus
28
A1
S A1
Out
Address bus
29
A2
S A2
Out
Address bus
30
A3
S A3
Out
Address bus
31
A4
S A4
Out
Address bus
32
A5
S A5
Out
Address bus
33
NC
NC
—
NC
34
A6
S A6
Out
Address bus
35
A7
S A7
Out
Address bus
36
A8
S A8
Out
Address bus
37
A9
S A9
Out
Address bus
38
A10
S A10
Out
Address bus
39
NC
NC
—
NC
40
A11
S A11
Out
Address bus
42
A13
S A13
Out
Address bus
43
A14
S A14
Out
Address bus
44
A15
S A15
Out
Address bus
2-5. Z80 CTC
1) Features
Four independently programmable counter/timer channels, each
with a readable downcounter and a selectable 16 or 256 prescaler.
Downcounters are reloaded automatically at zero count.
with a readable downcounter and a selectable 16 or 256 prescaler.
Downcounters are reloaded automatically at zero count.
Selectable positive or negative trigger initiates timer operation.
Three channels have Zero Count/Timeout outputs capable of driv-
ing Darlington transistors. (1.5mV @ 1.5V)
ing Darlington transistors. (1.5mV @ 1.5V)
NMOS version for cost sensitive performance solutions.
CMOS version for the designs requiring low power consumption
NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz.
CMOS Z84C3006 - DC to 6.17 MHz, Z84C3008 - DC to 8 MHz,
Z84C3010 - DC to 10 MHz
Z84C3010 - DC to 10 MHz
Interfaces directly to the Z80 CPU or—for baud rate generation—
to the Z80 SIO.
to the Z80 SIO.
Standard Z80 Family daisy-chain interrupt structure provides fully
vectored, prioritaized interrupts without external logic. The CTC
may also be used as an interrupt controller.
vectored, prioritaized interrupts without external logic. The CTC
may also be used as an interrupt controller.
6 MHz version supports 6.144 MHz CPU clock operation.
2) General description
The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-chan-
nel counter/timer can be programmed by system software for a broad
range of counting and timing applications. The four independently
programmable channels of the Z80 CTC satisfy common microcom-
puter system requirements for event counting, interrupt and interval
timing, and general clock rate generation.
System design is simplified because the CTC connects directly to
both the Z80 CPU and the Z80 SIO with no additional logic. In larger
systems, address decoders and buffers may be required.
nel counter/timer can be programmed by system software for a broad
range of counting and timing applications. The four independently
programmable channels of the Z80 CTC satisfy common microcom-
puter system requirements for event counting, interrupt and interval
timing, and general clock rate generation.
System design is simplified because the CTC connects directly to
both the Z80 CPU and the Z80 SIO with no additional logic. In larger
systems, address decoders and buffers may be required.
INTERNAL DATA BUS
ALU
REGISTER
ARRAY
ADDRESS
LOGIC AND
BUFFERS
16-BIT
ADDRESS BUS
8-BIT
DATA BUS
INSTRUCTION
REGISTER
DATA BUS
INTERFACE
INSTRUCTION
DECODER
CPU
TIMING
CPU
TIMING
CONTROL
+5V
GND
CLOCK
8 SYSTEMS
AND CPU
CONTROL
OUTPUTS
5 CPU
CONTROL
INPUTS
Figure 3. Z80C CPU Block Diagram
Programming the CTC is straightforward: each channel is pro-
grammed with two bytes: a third is necessary when interrupts are
enabled. Once started, the CTC counts down, automatically reloads
its time constant, and resumes counting. Software timing loops are
completely eliminated. Interrupt processing is simplified because only
one vector need be specified: the CTC internally generates a unique
vector for each channel.
The Z80 CTC requires a single +5% V power supply and the standard
Z80 single-phase system clock. It is packaged in 28-pin DIPs, a 44-
pin plastic chip carrier, and a 44-pin Quad Flat Pack. (Figures 2a, 2b,
and 2c). Note that the QFP package is only available for CMOS
versions.
grammed with two bytes: a third is necessary when interrupts are
enabled. Once started, the CTC counts down, automatically reloads
its time constant, and resumes counting. Software timing loops are
completely eliminated. Interrupt processing is simplified because only
one vector need be specified: the CTC internally generates a unique
vector for each channel.
The Z80 CTC requires a single +5% V power supply and the standard
Z80 single-phase system clock. It is packaged in 28-pin DIPs, a 44-
pin plastic chip carrier, and a 44-pin Quad Flat Pack. (Figures 2a, 2b,
and 2c). Note that the QFP package is only available for CMOS
versions.
3) Pin configuration
4) Functional description
The Z80 CTC has four independent counter/timer channels. Each
channel is individually programmed with two words: a control word
and a time-constant word. The control word selects the operating
mode (counter or timer), enables or disables the channel interrupt,
and selects certain other operating parameters. If the timing mode is
selected, the control word also sets a prescaler, which divides the
system clock by either 16 or 256. The time-constant word is a value
from 1 to 256.
channel is individually programmed with two words: a control word
and a time-constant word. The control word selects the operating
mode (counter or timer), enables or disables the channel interrupt,
and selects certain other operating parameters. If the timing mode is
selected, the control word also sets a prescaler, which divides the
system clock by either 16 or 256. The time-constant word is a value
from 1 to 256.
During operation, the individual counter channel counts down from
the preset time constant value. In counter mode operation the counter
decrements on each of the CLK/TRG input pulses until zero count is
reached. Each decrement is synchronized by the system clock. For
counts greater than 256, more than one counter can be cascaded. At
zero count, the down-counter is automatically reset with the time
constant value.
The timer mode determines time intervals as small as 2 s (8 MHz), 3
the preset time constant value. In counter mode operation the counter
decrements on each of the CLK/TRG input pulses until zero count is
reached. Each decrement is synchronized by the system clock. For
counts greater than 256, more than one counter can be cascaded. At
zero count, the down-counter is automatically reset with the time
constant value.
The timer mode determines time intervals as small as 2 s (8 MHz), 3
s (6 MHz), or 4 s (4 MHz) without additional logic or software timing
loops. Time intervals are generated by dividing the system clock with
a prescaler that decrements a preset down-counter.
Thus, the time interval is an integral multiple of the clock period, the
prescaler value (16 or 256), and the time constant that is preset in the
down-counter. A timer is triggered automatically when its time con-
stant value is programmed, or by an external CLK/TRG input.
Three channels have two outputs that occur at zero count.
The first output is a zero-count/timeout pulse at the ZC/TO output.
The fourth channel (Channel 3) does not have a ZC/TO output;inter-
rupt request is the only output available from Channel 3.
The second output is Interrupt Request (INT), which occurs if the
channel has its interrupt enabled during programming. When the Z80
CPU acknowledges Interrupt Request, the Z80 CTC places an inter-
rupt vector on the data bus.
The four channels of the Z80 CTC are fully prioritized and fit into four
configuous slots in a standard Z80 daisy-chain interrupt structure.
Channel 0 is the highest priority and Channel 3 the lowest. Interrupts
can be individually enabled (or disabled) for each of the four chan-
nels.
a prescaler that decrements a preset down-counter.
Thus, the time interval is an integral multiple of the clock period, the
prescaler value (16 or 256), and the time constant that is preset in the
down-counter. A timer is triggered automatically when its time con-
stant value is programmed, or by an external CLK/TRG input.
Three channels have two outputs that occur at zero count.
The first output is a zero-count/timeout pulse at the ZC/TO output.
The fourth channel (Channel 3) does not have a ZC/TO output;inter-
rupt request is the only output available from Channel 3.
The second output is Interrupt Request (INT), which occurs if the
channel has its interrupt enabled during programming. When the Z80
CPU acknowledges Interrupt Request, the Z80 CTC places an inter-
rupt vector on the data bus.
The four channels of the Z80 CTC are fully prioritized and fit into four
configuous slots in a standard Z80 daisy-chain interrupt structure.
Channel 0 is the highest priority and Channel 3 the lowest. Interrupts
can be individually enabled (or disabled) for each of the four chan-
nels.
5) Pin description
Pin
No.
Symbol
Signal
name
In/Out
Function
1
D0
S D0
In/Out
Data bus
2
D1
S D1
In/Out
Data bus
3
D2
S D2
In/Out
Data bus
4
D3
S D3
In/Out
Data bus
5
NC
NC
—
NC
6
NC
NC
—
NC
7
NC
NC
—
NC
8
D4
S D4
In/Out
Data busj*9
10
D6
S D6
In/Out
Data bus
11
NC
NC
—
NC
12
D7
S D7
In/Out
Data bus
13
GND
GND
—
GND
14
RD
S RDS
In
Read cycle status signal
15
NC
NC
—
NC
16
ZC/TO0
S TM0
Out
Zero count / Timeout signal
17
NC
NC
—
NC
18
ZC/TO1
NC
—
NC
19
ZC/TO2
NC
—
NC
20
NC
NC
—
NC
21
IORQ
S IORQ
In
Input / Output request signal
22
IEO
NC
—
NC
23
INT
S INT
Out
Interrupt request signal
24
NC
NC
—
NC
25
IEI
VCC
—
+5V
26
NC
NC
—
NC
27
M1
S M1
In
Machine cycle one signal
28
NC
NC
—
NC
29
CLK
CLK
In
System clock
30
NC
NC
—
NC
31
CE
S A6
In
Chip enable signal
32
RESET
S RES
In
Reset signal
33
CS0
S A0
In
Channelselect signal
34
NC
NC
—
NC
CLK
GND
CHANNEL
SIGNALS
SIGNALS
CTC
CONTROL
FROM
CPU
DAISY
CHAIN
INTERRUPT
CONTROL
CPU
DATA
BUS
ZC/TO0
CLK/TRG1
ZC/TO1
CLK/TRG2
ZC/TO2
CLK/TRG3
Z80 CTC
D1
D2
D3
D4
D5
D6
CS0
CS1
M1
IORQ
IEO
CLK/TRG0
RESET
INT
IEI
CE
RD
D0
D7
+5V
Figure 1. Pin Functions
1 1
1
23
33
NC
ZC/TO2
ZC/TO1
NC
ZC/TO0
NC
RD
GND
D7
IEO
IORQ
CLK/TRG3
CLK/TRG2
NC
NC
CLK/TRG1
CLK/TRG0
NC
+5V
NC
NC
CSI
34
44
2 2
1 2
CMOS
Z80 CTC
Figure 2c. 44-pin Quad Flat Pack Pin Assignments
Pin
No.
Symbol
Signal
name
In/Out
Function
35
CS1
S A1
In
Channelselect signal
36
CLK/TRG3
S TM1
In
External clock / timer signal
37
CLK/TRG2
S TM0
In
External clock / timer signal
38
NC
NC
—
NC
39
NC
NC
—
NC
40
CLK/TRG1
S INTS
In
External clock / timer signal
41
CLK/TRG0
VCC
In
+5V
42
NC
NC
—
NC
43
+5V
VCC
—
+5V
44
NC
NC
—
NC
2-6.
PD71037
DMA CONTROLLER
The PD71037 is a direct memory access controller (DMAC) for the
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to mem-
ory as well.
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to mem-
ory as well.
1) FEATURES
The clock speed is 10 MHz, twice that of the PD8237A-5 (clock
speed of 5 MHz).
speed of 5 MHz).
Each of the four DMA channels can be operated independently.
Each channel can be self-initialized.
Data is transferrable from memory to memory.
Data in memory can independently initialized by block.
High speed data transfer:
3.2 MB/sec. (clock seed of 10 MHz, normal transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
The number of DMA channels can directly be expanded
(Expansion mode).
(Expansion mode).
END input when data transfer is finished.
Software DMA request available.
CMOS
Low power consumption0
2) Pin configuration
3) Pin configuration
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
READY
READY
In
Ready signal
2
HLDAK
HLDAK
In
Hold acknowledge signal
3
ASTB
S ASTB
Out
Address strobe signal
4
AEN
S AEN
Out
Address enable signal
5
HLDRQ
HLDRQ
Out
Hold request signal
6
NC
NC
—
NC
7
CS
CS
In
Chip select signal
8
CLK
CLK
In
Clock
9
RESET
SRNRESET
In
Reset signal
10
DMAAK2
S DACK2
Out
DMA acknowlidge signal
11
DMAAK3
S DACK3
Out
DMA acknowlidge signal
12
DMARQ3
S DRQ3
In
DMA request signal
13
DMARQ2
S DRQ2
In
DMA request signal
14
DMARQ1
S DRQ1
In
DMA request signal
15
DMARQ0
S DRQ0
In
DMA request signal
16
GND
GND
—
GND
17
NC
NC
—
NC
18
A15/D7
S D7
In/Out Data bus
19
A14/D6
S D6
In/Out Data bus
20
A13/D5
S D5
In/Out Data bus
21
DMAAK1
S DACK1
Out
DMA acknowlidge signal
22
DMAAK0
S DACK0
Out
DMA acknowlidge signal
23
A12/D4
S D4
In/Out Data bus
24
A11/D3
S D3
In/Out Data bus
25
A10/D2
S D2
In/Out Data bus
26
A9/D1
S D1
In/Out Data bus
27
A8/D0
S D0
In/Out Data bus
28
NC
NC
—
NC
29
VDD
VCC
—
+5V
30
A0
S A0
In
Address bus
31
A1
S A1
In
Address bus
32
A2
S A2
In
Address bus
33
A3
S A3
In
Address bus
34
NC
NC
—
NC
35
END / TC
TC
In/Out End / Terminal cut signal
36
A4
S A4
In
Address bus
37
A5
S A5
In
Address bus
38
A6
S A6
In
Address bus
39
A7
S A7
In
Address bus
40
IORD
S IOR
In/Out I/O read signal
41
IOWR
S IOW
In/Out I/O write signal
42
MRD
S MRD
Out
Memory read signal
43
MWR
NC
—
NC
44
NC
NC
—
NC
READY
1
HLDAK
2
ASTB
3
AEN
4
HLDRQ
5
NC
6
CS
7
CLK
8
RESET
9
DMAAK2
1 0
DMAAK3
1 1
A3
33
A2
32
A1
31
A0
30
VDD
29
NC
28
A8/D0
27
A9/D1
26
A10/D2
25
A11/D3
24
A12/D4
23
µPD71037GB-3B4
2-7. MB62H149
1) Outline
The MB62H149 is a semi-custom LSI chip for the peripheral circuits
in the SRN (SHARP Retail Network), its main function is to communi-
cate data with the host CPU and control the peripheral circuits and
transmission control circuits of the Sub CPU (Z-80). Fig. 2. shows the
general configuration of the functions:
in the SRN (SHARP Retail Network), its main function is to communi-
cate data with the host CPU and control the peripheral circuits and
transmission control circuits of the Sub CPU (Z-80). Fig. 2. shows the
general configuration of the functions:
2) Internal functions
(1) Data handshaking circuit
Is used because data processing speeds vary and the timing of the
HOST CPU and SUB CPU do not synchronize, the MB62H149 is
used for data handshaking. When the data handshaking portion is
broken down, the system consists of a Write Signal from the HOST
CPU to the MB62H149, Read Signal from the MB62H149 of the SUB
CPU, Write Signal from the SUB CPU to the MB62H149 and Read
Signal from the MB62H149 of the HOST CPU, all of which from two
blocks as shown.
HOST CPU and SUB CPU do not synchronize, the MB62H149 is
used for data handshaking. When the data handshaking portion is
broken down, the system consists of a Write Signal from the HOST
CPU to the MB62H149, Read Signal from the MB62H149 of the SUB
CPU, Write Signal from the SUB CPU to the MB62H149 and Read
Signal from the MB62H149 of the HOST CPU, all of which from two
blocks as shown.
(2) Peripheral circuit
The peripheral circuit consists of an I/O address generation unit on
the SUB CPU, block dividing circuit, and the wait signal control unit.
the SUB CPU, block dividing circuit, and the wait signal control unit.
(a) I/O address generation circuit
A total of 11 I/O addresses are generated by A0, A1, A4, A5 and
RD and WR signals.
RD and WR signals.
(b) CPU and DMAC wait signal control unit
Clocks into the CPU (Z-80), SUB CPU and its peripheral LSI,
DMAC and CTC are operated respectively on 4 MHz.
While, the ADLC (MC68B54) (Advanced Data Link Control) is
operated by the E (Enable clock) of 2 MHz according to restric-
tions in terms of the hardware of the LSI.
It is necessary to synchronize the timing of the write and read in
the ADLC.
To control synchronization, timing, and input, the wait signal goes
into the CPU for CPU access and into the DMAC for DMA access.
This block is a circuit to generate such wait signal.
DMAC and CTC are operated respectively on 4 MHz.
While, the ADLC (MC68B54) (Advanced Data Link Control) is
operated by the E (Enable clock) of 2 MHz according to restric-
tions in terms of the hardware of the LSI.
It is necessary to synchronize the timing of the write and read in
the ADLC.
To control synchronization, timing, and input, the wait signal goes
into the CPU for CPU access and into the DMAC for DMA access.
This block is a circuit to generate such wait signal.
(c) Clock dividing circuit
This block divides the blocks according to the CLK supplied from
outside to generate the clock for CPU, DMAC and CTC and the E
and transmission clock rate (480 KBPS or 1 MBPS selectable) for
the ADLC.
outside to generate the clock for CPU, DMAC and CTC and the E
and transmission clock rate (480 KBPS or 1 MBPS selectable) for
the ADLC.
(3) Transmission control circuit
The transmission control circuit is divided into the modem unit, carrier
detect unit, collision detect unit.
detect unit, collision detect unit.
(a) Modem circuit
The transmission data input from the ADLC are PE modulated
(phase encoding modulation), the circuit to be output to the trans-
mission driver and the reception data input from the transmission
receiver are demodulated and produced at the ADLC.
(phase encoding modulation), the circuit to be output to the trans-
mission driver and the reception data input from the transmission
receiver are demodulated and produced at the ADLC.
(b) Collision detect circuit
The data transmitted from the home station is received and de-
tects a collision on the transmission line by means of an exclusive
OR gate.
tects a collision on the transmission line by means of an exclusive
OR gate.
(c) Carrier detect circuit
This circuit detects whether data is flowing on the transmission
line. It consists of a circuit which immediately senses a no data
status on the line. When data is not on the line the circuit functions
to sense an elapse of the fixed time rate. The immediate sensing
circuit is used for response testing and the delayed sensing circuit
is used for data testing.
The fixed time rate is selectable according to the transmission
speed as shown below via SRV-mode programming. Job #922.
line. It consists of a circuit which immediately senses a no data
status on the line. When data is not on the line the circuit functions
to sense an elapse of the fixed time rate. The immediate sensing
circuit is used for response testing and the delayed sensing circuit
is used for data testing.
The fixed time rate is selectable according to the transmission
speed as shown below via SRV-mode programming. Job #922.
Transmission speed
Delay time
1 MBPS
1.6m sec, 3.2m sec, 4.8m sec, 6.4m sec.
480 KBPS
3.2m sec, 6.4m sec, 9.6m sec, 12.8m sec.
MB62H149
Line
TRANS-
MISSION
CONTROL
CIRCUIT
MISSION
CONTROL
CIRCUIT
PERIPHERAL
CIRCUIT
CIRCUIT
DATA HAND
SHAKING
CIRCUIT
SHAKING
CIRCUIT
TIMER
COUNTER
COUNTER
SUB-CPU
(Z-80)
(Z-80)
DMAC
ADLC
HOST CPU
Fig. 2
HOST CPU
MB62H149
SUB CPU
Write
Read
(HOST CPU TO SUB CPU)
(FROM SUB CPU TO HOST CPU)
HOST CPU
MB62H149
SUB CPU
Write
Read
Fig. 3
HOST CPU
DATA BUS
(8bit)
DATA BUS
(8bit)
HOST CPU address
and RD, WR
and RD, WR
SUB CPU
DATA BUS
(8bit)
DATA BUS
(8bit)
HOST CPU · SUB CPU
& DMAC control
& DMAC control
HOST CPU
address
decode
address
decode
SUB CPU
write register
(HOST CPU
read register)
write register
(HOST CPU
read register)
HOST CPU
write register
(SUB CPU
read register)
write register
(SUB CPU
read register)
SUB CPU
write & HOST
CPU read control
unit (DMA &
CPU access)
write & HOST
CPU read control
unit (DMA &
CPU access)
HOST CPU
write & SUB
CPU read
control unit
(DMA & CPU
access)
write & SUB
CPU read
control unit
(DMA & CPU
access)
Fig. 4
CLK (16 MHz)
I/O address
Wait signal
SUB CPU address
& RD, WR
& RD, WR
SUB CPU address
decoding unit
decoding unit
CPU & DMAC wait
signal control unit
signal control unit
Clock dividing
circuit
circuit
System clock
(4 MHz)
(4 MHz)
Fig. 5
ADLC TDY
ADLC RDX
Collision detect
To transmission driver
From transmission receiver
Carrier detect 1
(for data)
(for data)
Carrier detect 2
(for resronse)
(for resronse)
MODEM unit
Collision
detect unit
detect unit
Carrier
detect unit
detect unit
Fig. 6
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