Sharp ER-A770 (serv.man4) Service Manual ▷ View online
2-10. ISP2032
This IC has been developed specially for UP-3300 to achieve VGA
CHIP and PSRAM interfaces.
CHIP and PSRAM interfaces.
Pin descriotion
Pin
No.
Name
I/O
Function
1
/VMEM
In
VIDEO MEMORY DECODE
C00000H C1FFFFH
16bit/8bit access, 8 bit read from the
CPU is treated as 16-bit on the VGA.
C00000H C1FFFFH
16bit/8bit access, 8 bit read from the
CPU is treated as 16-bit on the VGA.
2
/VMEM2
In
VIDEO MEMORY DECODE (ONLY FOR
GRAPHICS MODE; 8BIT)
C80000H C9FFFFH 8-bit access only.
/VMEM and /VMEM2 differ in their
apparent address to each other, but the
contents of memory to be accessed are
the same.
They differ in access method
(WORD/BYTE).
GRAPHICS MODE; 8BIT)
C80000H C9FFFFH 8-bit access only.
/VMEM and /VMEM2 differ in their
apparent address to each other, but the
contents of memory to be accessed are
the same.
They differ in access method
(WORD/BYTE).
3
/HWR
In
HIGH BYTE WRITE FROM CPU
4
/LWR
In
LOW BYTE WRITE FROM CPU
5
PHAI
In
CLOCK FROM CPU
6
VCC
7
/ISPEN
In
for ISP (In System Program)
8
/VWAITI
In
WAIT FROM VGA CHIP (IOCHRDY)
9
/VWAIT
Out
WAIT TO MPCA
There are following 2 ORs.
IOCHRDY from VGA CHIP
1 WAIT is generated when VRAM.
VGA I/O is accessed. (Because
IOCHRDY is slow, 1 WAIT is generated
prior to it.)
IOCHRDY is slow, 1 WAIT is generated
prior to it.)
10
/DWRI
In
DELAYED WRITE (FOR VGA CHIP
TIMING)
TIMING)
11
/DWRO
Out
WRITE FOR /DWRI
12
/DRDI
In
DELAYED READ (FOR VGA CHIP
TIMING)
TIMING)
13
/DRD
Out
READ FOR /PRDI
14
RES
Out
RESET OUTPUT
RESET
RESET
NOT (/RESET)
15
/RES
In
/RESET INPUT
16
A0
In
A0
17
GND
18
A20
In
A20
19
PCE21E
Out
EXTENDED PSRAM1 DECODE (EVEN)
800000H 8FFFFFH
800000H 8FFFFFH
20
PCE210
Out
EXTENDED PSRAM1 DECODE (ODD)
800000H 8FFFFFH
800000H 8FFFFFH
21
PCE220
Out
EXTENDED PSRAM2 DECODE (ODD)
900000H 9FFFFFH
900000H 9FFFFFH
22
PCE22E
Out
EXTENDED PSRAM2 DECODE (EVEN)
900000H 9FFFFFH
900000H 9FFFFFH
23
/IPLON0
In
IPL SIGNAL
24
/PSRF0
Out
PSRAM REFRESH
25
/OWR
Out
PSRAM WRITE (ODD SIDE)
26
/M3SWP
Out
MODE3 BUS SWAP (FOR PSRAM
ACCESS WHEN IPL)
ACCESS WHEN IPL)
27
Y2/SCLK
ISP
28
VCC
29
Y1/RESET
ISP
30
MODE
ISP
31
RASPN2E
In
EXTENDED PSRAM2 DECODE
(FROM MPCA)
800000H 9FFFFFH
(FROM MPCA)
800000H 9FFFFFH
Pin
No.
Name
I/O
Function
32
RASPN2
In
EXTENDED PSRAM2 DECODE
(FROM MPCA)
800000H 9FFFFFH
(FROM MPCA)
800000H 9FFFFFH
33
/RASPN12
In
PSRAM DECODE (FROM MPCA)
600000H 9FFFFFH
600000H 9FFFFFH
34
/AS
In
/AS FROM CPU
35
/RD
In
/RD FROM CPU
36
/RFSH
In
/RFSH FROM CPU
37
/SMEMR
Out
VIDEO MEMORY READ (TO VGA CHIP)
38
/SMEMW
Out
VIDEO MEMORY WRITE (TO VGA
CHIP)
CHIP)
39
GND
40
/COE0
Not used
41
/IORD
Out
VGA IO READ (TO VGA CHIP)
42
/IOWR
Out
VGA IO WRITE (TO VGA CHIP)
43
/SBHE
Out
BUS HIGH ENABLE (TO VGA CHIP)
44
/VIO2
Out
VGA IO CHIP SELECT
3. Address map
3-1. Total memory space
The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:
can see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
VRAM
RAM
ROM
Extended I/O area
000000h
0 page area
(64KB)
00FFFFh
200000h
600000h
C00000h
F00000h
FFFFFFh
Extended I/O area
(1MB)
(6MB)
(2MB)
Flash
RAM
(4MB)
VRAM
(1MB)
EP-ROM
D00000h
* The expanded I/O area means
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
* In the 0 page area, lower 64KB
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
Fig. 2
3-2. 0page area
The 0page area consists of four spaces: the ROM mapped area,
internal and external I/O areas.
The ROM mapped space have been devised for the following pur-
poses:
internal and external I/O areas.
The ROM mapped space have been devised for the following pur-
poses:
Simplifying the procedure for booting the IPL program
Achieving high-speed accessing, and accessing by abbreviated
instructions.
instructions.
3-3. I/O areas
The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
3-4. ROM space
Fig.5 shows the ROM space. The ER-A770 uses 2MB of NOR-type
flash memory instead of conventional ROM, so that the FROS1# from
the MPCA8 is input into the chip enable of the flash memory.
flash memory instead of conventional ROM, so that the FROS1# from
the MPCA8 is input into the chip enable of the flash memory.
3-5. VRAM & RAM space
The VRAM is the display memory of the LCD.
000000h
00FFFFh
00FF80h
00FE80h
Internal I/O area
External I/O area
ROM mapping area
I/O area
* The ROM area 200000h to
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
20FFFFh (ROS1 lower 64KB)
is mapped on the ROMmapping
area.
* The internal I/O area is used
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
for peripheral modules inside
the CPU; the external I/O area
is used for peripheral modules
outside the CPU.
For more information, refer to
the H8/510 hardware manual
and peripheral device
specification.
Fig. 3
00FE80h
00FF80h
00FFA0h
00FFB0h
00FFB4h
00FFB8h
00FFBCh
00FFC0h
00FFD0h
00FFE0h
00FFF0h
00FFFFh
Internal I/O area
MPCCS
MCR1Z
MCR2Z
OPCCS2
OPCCS1
T/PZ
Not used
OPTCSZ
Expanded MPC
(not used)
PRNZ (not used)
CPCSZ (not used)
TPRCI (not used)
* CPCSZ is CPC select for
Centronics Interface.
Centronics Interface.
* MPCCS and expanded MPC
signals are base signals for
MPCA8 internal register
decode. There is no external
signal.
signals are base signals for
MPCA8 internal register
decode. There is no external
signal.
* MCR1Z and MCR2Z are chip
select signals for the magnet
card reader.
(Use lower 2bytes.)
select signals for the magnet
card reader.
(Use lower 2bytes.)
* T/PZ is the internal decode
signal for USART built in
MPCA8. Thereis no external
signal. (Use lower 2bytes.)
signal for USART built in
MPCA8. Thereis no external
signal. (Use lower 2bytes.)
* OPCCS1 and OPCCS2
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
signals are decoded inside
the OPC (OPTION PERIP-
HERAL CONTROLLER)
using the option decode
signal OPTCS. There is no
external signal.
Fig. 4
200000h
(MAX4MB)
ROS1
5FFFFF
* Lower 64KB of the ROS1 is
mapped on the 0 page area.
mapped on the 0 page area.
* ROS1 is decoded by
MPCA8.
MPCA8.
Fig. 5
600000h
BFFFFFh
800000h
A00000h
D00000h
RAS1
VRAM
(2MB)
RAS2
(2MB)
(1MB)
* All the decode signals in the
area in the figure are supported
by MPCA8.
area in the figure are supported
by MPCA8.
* RAS1 signals from MPCA8
correspond to 2MB 600000h to
7FFFFFh.
correspond to 2MB 600000h to
7FFFFFh.
* OPTION RAM board (1MB and
2MB) interfaces using RAS2
as the base signal.
2MB) interfaces using RAS2
as the base signal.
* The actual VRAM is 512KB,
but it is accessed by every
128KB of bank according to
VGAC specification.
but it is accessed by every
128KB of bank according to
VGAC specification.
Fig. 6
3-6. Extended I/O area
The addresses from F00000h to FFFFFFh are called an extended I/O
area. The ER-A770 uses the following addresses as the break ad-
dress register (BAR) for SSP.
area. The ER-A770 uses the following addresses as the break ad-
dress register (BAR) for SSP.
FFFF00h FFFFFFh
4. LCD display
The ER-770 uses a 320 x 240 dot monochromatic LCD for the main
display and VGAC (MN89303A) for the display controller which is
connected to H8/510 in the ISA bus connection mode.
display and VGAC (MN89303A) for the display controller which is
connected to H8/510 in the ISA bus connection mode.
4-1. Block diagram
Here is the block diagram of the LCD and its allied components.
4-2. LCD panel
The LCD panel uses a dot-matrix liquid crystal module LM320153
with monochromatic STN and COFT backlight. The resolution is 320
x 240.
with monochromatic STN and COFT backlight. The resolution is 320
x 240.
4-3. Display controller
Matsushita VGAC (MN89303A) is used for display controller.
VRAM is on the address space of the CPU and data can be written
on and read from it by every 128 KB of bank at the address C00000H
on and read from it by every 128 KB of bank at the address C00000H
C1FFFFH from the CPU side. VRAM consists of 4 banks.
4-4. LCD ON control
The LCD’s is bias power supply is controlled by the MN89303A termi-
nal LCDON to turn the LCD screen on and off.
nal LCDON to turn the LCD screen on and off.
The LCDON is at "L" at resetting +5V power is supplied to the LCD by
setting the expanded function control register bit5 of MN89303A to
"H" with software. The LCD screen isn’t turned on until +5V is sup-
plied.
setting the expanded function control register bit5 of MN89303A to
"H" with software. The LCD screen isn’t turned on until +5V is sup-
plied.
4-5. Back light control
The back light is turned ON/OFF by the MN89303A terminal
BACKON. The initial value is "L" and the back light is off. By setting
the expanded function control register bit6 of MN89303A to "H", the
inverter unit is turned on.
BACKON. The initial value is "L" and the back light is off. By setting
the expanded function control register bit6 of MN89303A to "H", the
inverter unit is turned on.
4-6. Luminance and contrast adjustment
Luminance: Luminance is adjusted with an inverter which has dim-
ming function.
Contrast:
Contrast is adjusted by controlling the contrast adjust-
ment voltage (VCON) of the LM320153
ment voltage (VCON) of the LM320153
5. Customer display
The ER-770 can incorporate a UP-116DP (display tube unit for the
UP-P16DP) for the customer display to carry out the same control as
for the pole display (UP-P16DP).
UP-P16DP) for the customer display to carry out the same control as
for the pole display (UP-P16DP).
CPU
H8/510
RD#
WR#
SD0-15
SA0-16
IORD#
MEMRD#
IOWR#
MEMWR#
PHAI
CLK
WAIT#
RAS/CAS
WE#
MD0-15
MA0-9
RAS/CAS
WE#
D0-15
A0-9
VRAM
DRAM:512KB
LD0-3
LP
FP
DCLK
LD0-3
LP
FP
DCLK
LCD (320X240)
BACKLIGHT
VEE
BIAS
INVERTER
LCDON
BACKON
LCDWT
RFSH#
WAIT#
MPCA8
MN89303A
Fig. 7
6. Pseudo SRAM (Standard)
The device is TOSHIBA 4MB SRAM (TC51V8512AFT 512K 8bit) with
access time of 120ns.
access time of 120ns.
6-1. CPU interface
The figure below shows a typical pseudo SRAM interface in the ER-
A770.
A770.
6-2. Pseudo SRAM address
Standard SRAM is decoded as follows by the RASPN1 signal.
700000h 7FFFFFh
The base signal is 2MB. It thus wraparounds with 600000H
6FFFFFH 1MB.
Pseudo SRAM consists of 1 chip for respective even and odd number
addresses. Both of word and byte access from CPU are available.
6FFFFFH 1MB.
Pseudo SRAM consists of 1 chip for respective even and odd number
addresses. Both of word and byte access from CPU are available.
7. NOR-type flash memory
Here is the explanation for the interface of NOR-type flash memory.
The device is Sharp’s LH28F016SU flash memory which consists of
512 K words 16 or 1 MB 8, with 32 blocks of 64 KB.
The device is Sharp’s LH28F016SU flash memory which consists of
512 K words 16 or 1 MB 8, with 32 blocks of 64 KB.
7-1. CPU interface
The figure below shows a typical interface for the LH28F016SU of the
ER-A770 system.
ER-A770 system.
7-2. Device control
After resetting, the device automatically enters the array read mode
and perform the same action as the usual ROM, thus requiring no
special consideration when reading data.
and perform the same action as the usual ROM, thus requiring no
special consideration when reading data.
Data can be written at high speed by using the page buffer.
8. SSP control
The ER-A770 uses flash memory in the place of EPROM, so it is
possible to rewrite the contents of the flash memory in changing the
program. However, since the existing gate array MPCA8 is used, it is
also possible to use the conventional SSP.
possible to rewrite the contents of the flash memory in changing the
program. However, since the existing gate array MPCA8 is used, it is
also possible to use the conventional SSP.
8-1. Operation
Like the MPCA7, the MPCA8 adopts the break address register com-
parison method for detecting addresses. The operation of this method
is briefly explained below.
parison method for detecting addresses. The operation of this method
is briefly explained below.
The gate array always compares the break address register (BAR)
built in the gate array, with the address bus to monitor the address
bus.
built in the gate array, with the address bus to monitor the address
bus.
If both agree, the gate array outputs the NMI signal to the CPU, which
in turn shifts from normal handling to exception handling.
in turn shifts from normal handling to exception handling.
In both the MPCA7 and the MPCA8, SSP is achieved by the above
operation.
operation.
The setting of the break address register (BAR) is directly written in
the addresses from FFFF00h to FFFFFFh.
the addresses from FFFF00h to FFFFFFh.
9. Interrupt control
There are roughly two types of interrupts:
Internal interrupts: Controlled inside the CPU
External interrupts: Input into the CPU from outside
9-1. Internal interrupts
Device interrupts built in the CPU are used for the following applica-
tions:
tions:
Event factor
Application
SC11
Interrupt source as RS232 : CH8
SC12
Not used (SC1 is used for CKDC interface.)
FRT1
(ICI)
(OCRA)
(OCRB)
(OVF)
(OCRA)
(OCRB)
(OVF)
INTMCR MCR interrupt (to FT11 terminal)
FRT2
(ICI)
Standard SHEN event (for CKDC)
(OCRA)
Simple IRC timer event
(OCRB)
RS232 timer event
(OVF)
System timer (53 ms)
TMR
(CMA)
(CMB)
(OVF)
(CMB)
(OVF)
WDT
(OVF)
Drawer open timer
A/D
Not used
NMI
SSP request
9-2. External interrupts
The following types of external interrupts are available:
NMI (SSP)
IRQ0 (Standard I/O interrupt)
IRQ1 (RS232 interrupt)
IRQ2 (Not Used)
IRQ3 (Used as SCK terminal)
Odd side PSRAM
/OWR
A0
/HWR
/LWR
/RESET
/AS
/PCE1_O
/WSWAP
D7~D0
D15~D8
/WR
/CE
SD7~SD0
EVEN sid e PSRAM
Gate Arra y
RASPN1
A0
/RESET
/AS
/PCE1_E
/HWR
SD7~SD0
/WR
/CE
RASPN1E
RASPN1
/OE
.
/REFSH
RASPN1
or
RASPN2
or
RASPN2
/RASPN12
ISP2032
/RSWAP
REFSH
/RD
D
CLK
CLR
QB
Q
/PR
Fig. 8
RESET-
5V
FVPON
NORDY
H8/510
DATA
RD-
PORT64
PORT63
MPCA8
FROS1-
WE#
OE#
CE0#
GND
VPP
CE1#
RP#
3/5#
VCC
BYTE#
RY/BY#
A0~A2
DQ0~DQ1
WP#
LH28F
016SUT
016SUT
ADDRES
HWR-
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