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No.

Pin No.

Pin name

I/O

Pin

ER-A7RS

Description

55

29

TRQ2-

O

3S

NC

TIMER IRQ signal (INLINE)

56

11

D0

I/O

IOU

D0

DATA BUS (MAIN)

57

12

D1

I/O

IOU

D1

58

13

D2

I/O

IOU

D2

59

14

D3

I/O

IOU

D3

60

16

D4

I/O

IOU

D4

61

17

D5

I/O

IOU

D5

62

18

D6

I/O

IOU

D6

63

19

D7

I/O

IOU

D7

64

61

DB0

I/O

IOU

DB0

DATA BUS (USART)

65

62

DB1

I/O

IOU

DB1

66

63

DB2

I/O

IOU

DB2

67

64

DB3

I/O

IOU

DB3

68

66

DB4

I/O

IOU

DB4

69

67

DB5

I/O

IOU

DB5

70

68

DB6

I/O

IOU

DB6

71

69

DB7

I/O

IOU

DB7

72

21

A0

I

I

A0

ADDRESS BUS (MAIN)

73

22

A1

I

I

A1

74

23

A2

I

I

A2

75

24

A3

I

I

A3

76

25

A4

I

I

A4

77

26

A5

I

I

A5

78

10

OPTCS-

I

I

OPTCS-

OPTION CHIP SELECT (from MAIN)

79

31

RDO-

I

I

RDO-

READ signal (from MAIN)

80

30

WRO-

I

I

WRO-

WRITE signal (from MAIN)

81

9

RES-

I

IS

RES-

RESET signal (from MAIN)

82

34

R-

O

O

RDH-

READ signal (To USART)

83

37

W-

O

O

WRH-

WRITE signal (To USART)

84

51

RES

O

O

RES USART

RESET signal (To USART)

85

92

X1

O

X1

Oscillation circuit

86

91

X2

I

X2

87

53

XOUT

O

O

CLK USART

Clock for USART 

88

8

TRCK

O

O

NC

T/R clock for 1CH USART

89

35

AB0

O

O

AH0

Address bus for USART

90

33

AB1

O

O

AH1

91

85

USICH

I

ISC

GND

UNIT3 USART 1CH/2CH select

92

50

PX

O

PX

Power source clock

93

39

VCC

VCC

94

89

VCC

VCC

95

15

GND

GND

96

40

GND

GND

97

65

GND

GND

98

90

GND

GND

99

49

RTS0-

O

O

RTS1-

RS-232 control signal RTS- output

100

44

RTS1-

O

O

RTS2-

ICU : CMOS level input (internal pullup resistor)
O

:  Output

IS

: TTL level input (internal schmit circuit)

ISC : CMOS level input (internal schmit circuit)
3S

: Three state output

IOU : I/O port (internal pullup resistor)

– 4 –

The MB89371A (Serial data transmitter/receiver, 2 units) is a
versatile-use interface LSI for communication lines, which is
equipped with two sets of equivalent units of the MB89251A (serial
data transmitter/receiver), the baud rate generating section, and the
interruption adjustment section. 

It is positioned between the line Modem and the computer, and used
for serial/parallel conversion of data, data send/receive operation
check, and the synchronization mode selection according to the
program assignment. 

The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and
transmits them. In the synchronization mode, it transmits
synchronization characters during no transmission data period. In the
advancement synchronization mode, it allows selection of
transmission clocks and transmission baud rates. 

The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted. 

In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations with
the transmitter side. In the advancement synchronization mode, it
allows selection of transmission clocks and reception baud rates. 

The baud rate generating section generates clock pulse signals
which are used in transmission and reception and delivered through
the baud rate selecting section to the SDTR section. 

It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check. 

l

Two independent channels of SDTR.

l

Built-in baud rate generator which allows setting for each channel

l

External clock available

l

Internal clock output available. 

l

Maskable interruption generating circuit

l

Two channels are assigned to different address spaces. 

l

Baud rate DC ~ 240K baud (with external clocks)

l

Full duplex communication

l

Program assignment in synchronization mode

•

Data bit length: 5 - 8 bits

•

Character synchronization system: Internal synchronization, 
external synchronization

•

Number of synchronized characters: Single character, double
characters

•

Parity occurrence and check: parity valid/invalid 

even parity, odd parity

l

Operations in the synchronization mode  

•

Overrun error and parity error detection

•

Transmit/receive buffer state acknowledgment

•

Synchronization character detection

•

Automatic insertion of synchronization character 

l

Program assignment function in the advancement synchronization
mode

•

Data bit length: 5 ~ 8 bits

•

Stop bit length: 1, 1

1

⁄

2

, 2 bits

•

Baud rate: Transmission clock, reception clock x 1, x 1/16, x
1/64

•

Parity occurrence and check: Parity valid, invalid 

Even parity, odd parity

l

Operations in the advancement synchronization mode

•

Detection of framing error, overrun error, parity error 

•

Transmission/reception buffer state acknowledgment

•

Break characters detection

l

Error start bit detection

l

IBM Bi-sync system operation allowed.

l

Duplex buffer system in the transmission and the reception
sections. 

l

Loop back diagnostic functions

l

I/O signal level TTL compatible

l

Compatible with standard microprocessor in connecting pins and
signal timing.

l

Standard 42 pin plastic DIP, 48 pin plastic QFP

l

+5V single power source

1

DB4

2

DB5

3

DB6

4

DB7

5

TRNCLK1

6

W

7

CS1

8

RSLCT0

9

R

10

RCVRDY1

11

RSLCT1

12

CS2

36

RTS1

35

DSR1

34

RST

33

CLOCK

32

TRNDT1

31

TRNEMP1/ST1-1

30

CTS1

29

SYNC/BRK1

28

TRNRDY1

27

RCVCLK2

26

DTR2

25

RTS2

DB0~DB7

CS1,CS2

RSLCT0,RSLCT1

W,R

TRNRDY1

RCVRDY1

SYNC,BRK1

TRNEMP1

RST

TRNRDY 2

RCVRDY 2

SYNC/BRK2

TRNEMP2

CLOCK

SDTR1

TRNDT1

RTS1
DTR1

RCVDT1
CTS1

DSR1

TRNCLK1
RCVCLK1

SDTR2

TRNDT2
RTS2
DTR2

RCVDT2

CTS2

DSR2

TRNCLK2

RCVCLK2

Address

decoder

Mode setting

register 1

Baud rate

setting

register 1

Baud rate

generator

Mode setting

register 2

Baud rate

setting

register 2

Interrup-

tion

mask 1

Loop
back

control

1

Loop
back

control

2

Interrup-

tion

mask 2

Clock

control

1

Clock

control

2

VCC

GND

– 5 –

No.

Pin No.

Pin name

I/O

ER-A7RS

Data bus

1

1

DB4

I/O

DB4

2

2

DB5

I/O

DB5

3

3

DB6

I/O

DB6

4

4

DB7

I/O

DB7

5

41

DB0

I/O

DB0

6

42

DB1

I/O

DB1

7

44

DB2

I/O

DB2

8

45

DB3

I/O

DB3

9

46

RCVDT1

I

RCVDT1

RS-232 reception data signal

10

13

RCVDT2

I

RCVDT2

11

47

GND

–

GND

12

5

TRNCLK1-

I

GND

Data transmission clock

13

15

TRNCLK2-

I

GND

14

6

W-

I

WRH-

Write signal

15

7

CS1-

I

CS1-

RS-232 chip select

16

12

CS2-

I

CS2-

17

8

RSLCT0

I

AH0

Address bus

18

11

RSLCT1

I

AH1

19

9

R-

I

RDH-

Read signal

20

10

RCVRDY1

O

RCVRDY1

RS-232 data reception enable signal

21

16

RCVRDY2

O

RCVRDY2

22

28

TRNRDY1

O

TRNRDY1

RS-232 data transmission enable signal

23

17

TRNRDY2

O

TRNRDY2

24

29

BRK1

O

BRK1

Break code detection signal

25

18

BRK2

O

BRK2

26

30

CTS1-

I

(CTS1-)GND

RS-232 clear to send signal

27

20

CTS2-

I

(CTS2-)GND

28

31

TRNEMP1

O

TRNEMP1

RS-232 transmission buffer empty signal

29

21

TRNEMP2

O

TRNEMP2

30

14

NC

–

NC

31

24

NC

–

NC

32

38

NC

–

NC

33

48

NC

–

NC

34

19

OPEN

NC

35

43

OPEN

NC

36

32

TRNDT1

O

TXD1

RS-232 transmission data signal

37

22

TRNDT2

O

TXD2

38

35

DSR1-

I

DSR1-

RS-232 data set ready signal

39

23

DSR2-

I

DSR2-

40

36

RTS1-

O

NC

Request to send signal

41

25

RTS2-

O

NC

42

37

DTR1-

O

DTR1-

RS-232 data terminal ready signal

43

26

DTR2-

O

DTR2-

44

39

RCVCLK1-

I

GND

Data reception clock

45

27

RCVCLK2-

I

GND

46

33

CLOCK

I

CLK USART

Clock signal

47

34

RST

I

USART

RESET signal

48

40

VCC

–

VCC

+5V

– 6 –

No.

Pin No.

Pin name

I/O

ER-A7RS

Data bus

1

1

DB4

I/O

D4

2

2

DB5

I/O

D5

3

3

DB6

I/O

D6

4

4

DB7

I/O

D7

5

41

DB0

I/O

D0

6

42

DB1

I/O

D1

7

44

DB2

I/O

D2

8

45

DB3

I/O

D3

9

46

RCVDT1

I

RDD1

Track1 data signal

10

13

RCVDT2

I

RDD2

Track2 data signal

11

47

GND

–

GND

12

5

TRNCLK1-

I

NC

Data transmission clock

13

15

TRNCLK2-

I

NC

14

6

W-

I

WR-

Write signal

15

7

CS1-

I

MCR1S-

Track1 select signal 

16

12

CS2-

I

MCR2S-

Track2 select signal

17

8

RSLCT0

I

A0

Address bus

18

11

RSLCT1

I

A1

19

9

R-

I

RD-

Read signal

20

10

RCVRDY1

O

RDY1

RS-232 data  reception enable signal

21

16

RCVRDY2

O

RDY2

22

28

TRNRDY1

O

NC

23

17

TRNRDY2

O

NC

24

29

BRK1

O

NC

25

18

BRK2

O

NC

26

30

CTS1-

I

GND

27

20

CTS2-

I

GND

28

31

TRNEMP1

O

NC

29

21

TRNEMP2

O

NC

30

14

NC

–

NC

31

24

NC

–

NC

32

38

NC

–

NC

33

48

NC

–

NC

34

19

OPEN

NC

35

43

OPEN

NC

36

32

TRNDT1

O

NC

37

22

TRNDT2

O

NC

38

35

DSR1-

I

CLS1-

Track1 card detecting signal

39

23

DSR2-

I

CLS2-

Track2 card detecting signal

40

36

RTS1-

O

NC

41

25

RTS2-

O

NC

42

37

DTR1-

O

NC

Data terminal ready signal

43

26

DTR2-

O

NC

44

39

RCVCLK1-

I

RCP1

Track1 clock pulse signal 

45

27

RCVCLK2-

I

RCP2

Track2 clock pulse signal

46

33

CLOCK

I

USART

Clock signal

47

34

RST

I

USART

RESET signal

48

40

VCC

–

VCC

+5V

– 7 –