Sharp UP-800 (serv.man25) Service Manual ▷ View online
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 10
■ Signal name descriptions
6. POWER SOURCE
RCP1
Track 1 clock pulse
RDD1
Track 1 data signal
CLS1
Track 1 card detection signal
RCP2
Track 2 clock pulse
RDD2
Track 2 data signal
CLS2
Track 2 card detection signal
RCP3
Track 3 clock pulse
RDD3
Track 3 data signal
CLS3
Track 3 card detection signal
RCVRDY1
Track 1 data receive detection signal
RCVRDY2
Track 2 data receive detection signal
RCVRDY3
Track 3 data receive detection signal
MCRINT#
Interrupt signal by OR-composition of RCVRDY and SYNC input
DC 36
㨪42V
UNREG
3.3V
1.5V
2.5V
1.2V
5V, 5.7V
2.7V
LOW
LOW
QUISCENT
EC31QS06
3.3V (CPU I/O, VDD-CPG, FPGA I/O,
other peripheral LOGIC ) MAX 350mA
3.3VB (SRAM, CKDC)
EC31QS06
5V (PRINTER IF 60+24mA)
20DP : 1A, RS232C* 2ch : 200mA
EC31QS06
1.5V (CPU CORE ) 730mA
2.5V (FPGA VCCAUX ) 50m
1.2V (FPGA VCCINT) 50m
3.6V
BATTERY
24V
24V (DRAWER)
POWER MONITOR POINT
POWER
MONITOR POINT
MONITOR POINT
5.7V (POPUP DISPLAY 500mA)
12V
12V (INVERTER)
VP (PRINTER)
ON/OFF CONTROLL (FPGA)
ON/OFF CONTROLL (Different from INVERTER ON/OFF)
EC31QS06
ON/OFF CONTROLL
BA33DD0T
BA15DD0WHFP
LM2574N+BOOST Tr.
PQ1CG2032
LM2574HVN + BOOST Tr.
3.3VL(LCD 165mA)
3.3V
ON/OFF
CONTROLL (CPU : VCPWC)
ON/OFF CONTROLL
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 11
7. RESET
7-1. CIRCUIT COMPOSITION
CK D C X
C KDCR
STOP #
PO FF #
SR ES #
CP U
PTB5
MRESET#
RESET#
TRST#
IR L0#
DONE
HD I_TRST #
FPG A
DONE
PRO G _B
IN IT _ B
R ESE T#
XCF 2 S
POFF #
FL ASH
RESET#
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 12
7-2. OPERATION FLOW
■ Power ON / CKDC reset (Reset switch: Neighborhood of the expansion SRAM socket)
■ Power OFF
8. INTERRUPTION
The interruption is as shown below.
■ CPU port
■ FPGA
*For USART, UART, and software interruption, refer to the item of the
FPGA.
POFF# cancel
NO
YES
CKDC sleep
Power ON
CKDC reset
CKDC boot
CKDC system reset cancel
FPGA configuration
FPGA DONE rising
CPU reset cancel
STOP# generates ?
Standby
POF detection
(CKDC,CPU)
YES or when STOP# does not generate for 100ms.
CKDC system reset execution
NO (up to 100ms)
CPU
I/O
External
signal name
Remark
IRL2
I
TOUCH_INT#
TOUCH PANEL INTRRUPT
IRL1
I
FPGAINT#
FPGA INTRRUPTUSART, UART,
CKDC, SOFT INT, LAN, MCR
CKDC, SOFT INT, LAN, MCR
IRL0
I
POFF#
POFF# signal
CMT/CTR3
I
CKDC_SHEN#
SHEN# signal
CMT/CTR3
I
MCRINT#
MCRINT# signal
FPGA
I/O
External
signal name
Remark
EXINT1#
I
KRQ#
CKDC interruption
EXINT2#
I
LANINT#
LAN controller interruption
EXINT3#
I
MCRINT#
MCR interruption
EXINT4#
I
SHEN#
CKDC SHIFT ENABLE
UP-800F/810F (V)
UP-I04EF HARD DESCRIPTION
6 – 1
CHAPTER 6. UP-I04EF HARD DESCRIPTION
1. BLOCK DIGRAM
2. CPU (D6413003)
(1) Pin configuration
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