Sharp UP-800 (serv.man25) Service Manual ▷ View online
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 6
5-7. INVERTER
The inverter is turned ON/OFF by the GPIO27 of FPGA. (On at H)
It is provided with the light control function, which is controlled with the
general-purpose ports 0, 1, 2, and 3 of CKDCx.
general-purpose ports 0, 1, 2, and 3 of CKDCx.
(In the D/A conversion by the R-2R ladder, P03 side is used for MSB.)
* After setting the light control data, turn on the inverter.
* The upper limit of the light control data is “D”.
■ Related FPGA port
5-8. TOUCH PANEL IF
A touch panel of 4-wire type and 6.5 inch made by Fujitsu is employed.
Touch panel controller : The AK4182A made by Asahi Kasei is con-
nected to SPI of the CPU.
nected to SPI of the CPU.
For details, refer to the Specifications of the AK4182A.
■ Related CPU ports
5-9. FPGA
This is composed of the following blocks.
• 16450 for the RS232C (5CH is for the UP-P20DP (RS232C).)
×
6
• Timer using BAUDOUT of 16450as the clock source,
×
6
8251 for the MCR,
×
3
• Interrupt control, GPID (16 lines)
• 16.6667MHz is supplied from the outside for use as the base clock.
FPGA pin
I/O
Signal name/Description
GPIO27
O
INVPON (INVERTER POWER It do on in H)
CPU pin
I/O
Signal name / Description
HSPI_TX / SIM_D / MCDAT
O
TOUCH_TX
HSPI_CLK / SIM_CLK / MCCLK
O
TOUCH_CLK
HSPI_RX
I
TOUCH_RX
HSPI_CS / SIM_RST / MCCMD
O
TOUCH_CS#
HAC_BIT_CLK0 (PTJ7)
I
TOUCH_BUSY
GPIO : PTJ7
GPIO : PTJ7
IRL2
I
TOUCH_INT#
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 7
(1) Pin arrangement
No.
Pin name
I/O
CS5#
I
A7
I
A6
I
A5
I
A4
I
A3
I
A2
I
A1
I
A0
I
D7
I/O
D6
I/O
D5
I/O
D4
I/O
D3
I/O
D2
I/O
D1
I/O
D0
I/O
RESET#
I
WR#
I
RD#
I
16.6667MHz
I
SOUT1
O
SIN1
I
DSR1
I
DTR1
O
CTS1
I
RTS1
O
DCD1
I
RI1
I
SOUT2
O
SIN2
I
DSR2
I
DTR2
O
CTS2
I
RTS2
O
DCD2
I
RI2
I
SOUT3
O
SIN3
I
DSR3
I
DTR3
O
CTS3
I
RTS3
O
DCD3
I
RI3
I
SOUT4
O
SIN4
I
DSR4
I
DTR4
O
CTS4
I
RTS4
O
DCD4
I
RI4
I
SOUT5
O
SIN5
I
DSR5
I
DTR5
O
CTS5
I
RTS5
O
DCD5
I
RI5
I
MCRINT#
O
MCRINT
O
RDD1
I
RCP1
I
CLS1
I
RDD2
I
RCP2
I
CLS2
I
RDD3
I
RCP3
I
CLS3
I
RCVDT1#
I
RCVDT2#
I
RCVDT3#
I
RCVDT4#
I
RCVDT5#
I
EXINT1#
I
EXINT2#
I
EXINT3#
I
EXINT4#
I
FIRQ#
O
GPIO1
I/O
GPIO2
I/O
GPIO3
I/O
GPIO4
I/O
GPIO5
I/O
GPIO6
I/O
GPIO7
I/O
GPIO8
I/O
GPIO9
I/O
GPIO10
I/O
GPIO11
I/O
GPIO12
I/O
GPIO13
I/O
GPIO14
I/O
No.
Pin name
I/O
GPIO15
I/O
GPIO16
I/O
GPIO17
I/O
GPIO18
I/O
GPIO19
I/O
GPIO20
I/O
GPIO21
I/O
GPIO22
I/O
GPIO23
I/O
GPIO24
I/O
GPIO25
I/O
GPIO26
I/O
GPIO27
I/O
GPIO28
I/O
GPIO29
I/O
GPIO30
I/O
GPIO31
I/O
GPIO32
I/O
118
FPGA_A0
I
No.
Pin name
I/O
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 8
(2) CKDC (Clock, Key, Rear display, Clerk)
The control method of the key, the rear display, and the clerk is the same as that of the UP-600/700.
The CKDC is the new - type CKDC compatible with the old - type CKDC of Hitachi. (For some, the command of Not Used is omitted.)
(3) EFT
It is provided with the UP-104EF compatible with the ER-03EF.
The command system is perfectly compatible with the UP-104EF.
The command system is perfectly compatible with the UP-104EF.
When the UP-I04EF is installed, CH! Of the RS232C is used only for the
EFT.
■ Register composition
Caution: Data write to DTR is allowed when “CLM : 1/IBF : 0”.
Data read from DTR is allowed when “OBF : 1”.
(4) Printer
For details, refer to the predications of the LT1320CS.
■ Related CPU ports
■ Related FPGA ports
CK D C X
SC K
HTS
ST H
KRQ #
SHEN #
STOP #
SRES #
PO 0 - 3
CP U
PT B7
PT B5
RESE T#
Keyboard
Rea r display
LED 7 seg. 7 digits
SCIF1_TXD
SCIF1_CLK
SCIF1_RXD
IRL0#
Inverter
(Lightcontrol)
(Lightcontrol)
Contact-less clerk
DONE (FPGA)
Address
Name
H’1440000E DTR
(Data register)
Used for data send/receive with the
EFT I/F CPU.
EFT I/F CPU.
When WRITE
When READ
When READ
: Machine
3 EFT
: EFT
3 Machine
READ/WRITE may be performed only
when the Caution are satisfied.
when the Caution are satisfied.
H’1440000F
STR
(Status register)
(Status register)
Used for data send/receive with the
EFT I/F CPU.
EFT I/F CPU.
D7 D6 D5 D4 D3 D2 D1 D0
䌘
䌘
䌘
䌘
䌘 CLM
IBF
OBF
䌘 䋺 Not determined
Data to HOST CPU
1
1
䋺 Yes 0䋺 No
Data to SUB CPU
1
1
䋺 Yes 0䋺 No
SUB CPU data read
1
1
䋺 Not reading
0
䋺 Reading
CPU pin
I/O
Signal name / Description
SCIF0_CLK
O
PCLK (PRINTER CLOCK)
SCIF0_TXD
O
PSO (PRINTER DATA)
UCLK (PTH2)
O
PLATCH#
AN1
I
VPRNT : Printer voltage
(The A/D value is 1/10 of the voltage.)
(The A/D value is 1/10 of the voltage.)
AN0
I
HTEMP : Head temperature
(For the constant B, refer to the printer specifica-
tions.)
(For the constant B, refer to the printer specifica-
tions.)
FPGA pin
I/O
Signal name / Description
GPIO1
O
JAS/MSTEP1 (PRINTER MOTOR drive signal)
GPIO2
O
JDS/MSTEP2 (PRINTER MOTOR drive signal)
GPIO3
O
RAS/MSTEP3 (PRINTER MOTOR drive signal)
GPIO4
O
RDS/MSTEP4 (PRINTER MOTOR drive signal)
GPIO5
O
JMOTOFF (PRINTER MOTOR OFF 1)
GPIO7
O
JMOTCUP (PRINTER MOTOR CURRENT UP)
GPIO9
I
JPES# (JOURNAL PAPER END SENDOR)
GPIO11
I
PHUPS (PRINTER HEAD UP)
GPIO12
I
ACUTSW (AUTO CUTTER SW)
GPIO17
O
VHCOM (The printer power ON at H)
GPIO18
O
STRB1#
GPIO19
O
STRB2#
GPIO20
O
STRB3#
GPIO21
O
STRB4#
GPIO22
O
ACUT1
GPIO23
O
ACUT2
GPIO26
O
PRINTER SENSOR ON
UP-800F/810F (V)
HARDWARE DESCRIPTION
5 – 9
(5) SD card IF
This is controlled by using the SCIF2 of the CPU.
■ CPU ports
(6) RS232C IF
This is provided with general-purpose ports of CH1-CH4 and the port
exclusive for 20DP.
exclusive for 20DP.
*When the UP-I04EF is installed, CH1 is the port exclusive for EFT.
*The applicable baud rates are as shown below:
1200bps /2400bps / 3600bps / 4800bps /9600bps / 19200bps /
38400bps / 57600bps / 115200bps / 56000bps is inhibited.
38400bps / 57600bps / 115200bps / 56000bps is inhibited.
(7) MCR
The MCR of 3 tracks is optionally available.
CPU pin Name
External
signal name
Remark
SCIF2_CLK
SDCLK
SD clock signal
SCIF2_TXD
SDTXD
SD data send signal
SCIF2_RXD
SDRXD
SD data receive signal
AUDSYNC
(GPIO : PTK3)
(GPIO : PTK3)
SDPOWER#
SD power control signal
ADTRG#/
AUDATA [0]
(GPIO : PTK2)
AUDATA [0]
(GPIO : PTK2)
SDCS#
SD chip select signal
AUDCK
(GPIO : PTK4)
(GPIO : PTK4)
SDWP#
SD write protect signal
AUDATA [1]
(GPIO : PTK5)
(GPIO : PTK5)
SDDTCT#
SD card insertion/non-insertion
sense signal
sense signal
Channel
Connector
Purpose
CH1
RJ-45
General
CH2
RJ-45
General
CH3
D-SUB 9PIN
General / For the scanner
(Poser supply required)
(Poser supply required)
CH4
D-SUB 9PIN
General / When 04EF is con-
nected, the exclusive port for
EFT.
nected, the exclusive port for
EFT.
CH5 port for 20DP
RJ-45
Exclusive for 20DP
(Poser supply required)
(Poser supply required)
CH6
RJ-45
General
8251
㬍3
R C P 1
R D D 1
C L S 1
R C P 2
S H 7 7 60
R D D 2
C L S 2
R C P 3
IR L 1
R D D 3
C M T _C T R 1
C L S 3
EX IN T 3#
MCRINT#
EXINT3#
FPGAINT#
Interrupt controller
FPGA
RCVRD Y 1
RCVRD Y 2
RCVRD Y 3
RCVRD Y 1
RCVRD Y 2
RCVRD Y 3
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