Sharp UP-800 (serv.man19) Service Manual ▷ View online
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 5
5-5. LAN CONTROLLER
LAN9118Rev.C is used.
The MAC address is saved in the EEPROM (93LC46A) .
■ LANC connection
5-6. LCD
TFT6.5INCH LG PHILIPS LB065WQ3 is used.
The VRAM commonly uses the SDRAM area.
The LCD displays in 64K colors (RGB5-6-5 bit. 16bpp)
■ Connection
Pin name
(Signal
name)
I/O
Pin Number
Function
D [31:16]
IO
21 - 26, 29 - 33,
36 - 40
36 - 40
Host Data High
D [15:0]
IO
43 - 46, 49 - 53,
56 - 59, 62 - 64
56 - 59, 62 - 64
Host Data Low
A [7:1]
I
12 - 18
Address
nRD
I
92
Read strobe
nWR
I
93
Write strobe
nCS
I
94
Chip select
IRQ
O/OD
72
Interrupt
Reserved
-
71, 73, 75, 84
Reserved
SPEED_SEL
I (PU) 74
100M/10M default
FIFO_SEL
I
76
FIFO Select
TPO+
AO
79
Twisted Pair Transmit
Output, Positive
Output, Positive
TPO-
AO
78
Twisted Pair Transmit
Output, Negative
Output, Negative
TPI+
AI
83
Twisted Pair Receive Input,
Positive
Positive
TPI-
AI
82
Twisted Pair Receive Input,
Negative
Negative
EXRES1
AI
87
PHY external bias resistor
EEDIO,
D32/nD16
D32/nD16
IO
67
EEPROM Data /
Data bus width select
Data bus width select
nEECS
O
68
EEPROM chip select
EECLK
O
69
EEPROM clock
XTAL1
I
6
25MHz crystal input
XTAL2
O
5
25MHz crystal input
nRESET
I (PU) 95
Reset
PME
O
70
Wakeup Indicator
LED3/GPOI2
OD/O/I 100
Full duplex indicator
LED2/GPIO1
OD/O/I 99
Link & Activity indicator
LED1/GPIO0
OD/O/I 98
Speed (100M /10M)
indicator
indicator
RBIAS
AI
10
PLL Bias
ATEST
I
9
Test Pin
VREG
P
2
Power source for Internal
regulator
regulator
VDD_IO
P
20, 28, 35, 42,
48, 55, 61, 97
48, 55, 61, 97
I/O Power
GND_IO
P
19, 27, 34, 41,
47, 54, 60, 96
47, 54, 60, 96
I/O GND
VDD_A
P
81, 85, 89
Analog Power
VDD_A_RB
P
91
Analog Power,
Rev.B is NC (OPEN)
Rev.B is NC (OPEN)
VSS_A
P
77, 80, 86, 88
Analog GND
VSS_A_RB
P
90
Analog GND,
Rev.B is NC (OPEN)
Rev.B is NC (OPEN)
VDD_CORE
P
3, 65
Core voltage decoupling
GND_CORE
P
1, 66
Core GND
VDD_PLL
P
7
PLL Power
VSS_PLL
P
4
PLL GND
VDD_REF
P
8
Reference Power
VSS_REF
P
11
Reference GND
CPU
External
connection
LCD
VCPWC controls
ON/OFF of the power IC.
ON/OFF of the power IC.
3.3VL
VDD
GND
GND
LCD_FLM
VSYNC
VS
LCD_M_DISP
DE
DE
LCD_CL1
HSYNC
HS
LCD_DATA4
B5
B5
LCD_DATA3
B4
B4
LCD_DATA2
B3
B3
LCD_DATA1
B2
B2
LCD_DATA0
B1
B1
GND
B0
LCD_DATA10
G5
G5
LCD_DATA9
G4
G4
LCD_DATA8
G3
G3
LCD_DATA7
G2
G2
LCD_DATA6
G1
G1
LCD_DATA5
G0
G0
LCD_DATA15
R5
R5
LCD_DATA14
R4
R4
LCD_DATA13
R3
R3
LCD_DATA12
R2
R2
LCD_DATA11
R1
R1
GND
R0
LCD_CL2
(BCLK : 8.33MHz by
dividing 33.33MHz into 4.)
(BCLK : 8.33MHz by
dividing 33.33MHz into 4.)
DOTCLK
DCLK
Pin name
(Signal
name)
I/O
Pin Number
Function
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 6
5-7. INVERTER
The inverter is turned ON/OFF by the GPIO27 of FPGA. (On at H)
It is provided with the light control function, which is controlled with the
general-purpose ports 0, 1, 2, and 3 of CKDCx.
general-purpose ports 0, 1, 2, and 3 of CKDCx.
(In the D/A conversion by the R-2R ladder, P03 side is used for MSB.)
* After setting the light control data, turn on the inverter.
* The upper limit of the light control data is “D”.
■ Related FPGA port
5-8. TOUCH PANEL IF
A touch panel of 4-wire type and 6.5 inch made by Fujitsu is employed.
Touch panel controller : The AK4182A made by Asahi Kasei is con-
nected to SPI of the CPU.
nected to SPI of the CPU.
For details, refer to the Specifications of the AK4182A.
■ Related CPU ports
5-9. FPGA
This is composed of the following blocks.
• 16450 for the RS232C (5CH is for the UP-P20DP (RS232C).)
×
6
• Timer using BAUDOUT of 16450as the clock source,
×
6
8251 for the MCR,
×
3
• Interrupt control, GPID (16 lines)
• 16.6667MHz is supplied from the outside for use as the base clock.
FPGA pin
I/O
Signal name/Description
GPIO27
O
INVPON (INVERTER POWER It do on in H)
CPU pin
I/O
Signal name / Description
HSPI_TX / SIM_D / MCDAT
O
TOUCH_TX
HSPI_CLK / SIM_CLK / MCCLK
O
TOUCH_CLK
HSPI_RX
I
TOUCH_RX
HSPI_CS / SIM_RST / MCCMD
O
TOUCH_CS#
HAC_BIT_CLK0 (PTJ7)
I
TOUCH_BUSY
GPIO : PTJ7
GPIO : PTJ7
IRL2
I
TOUCH_INT#
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 7
(1) Pin arrangement
No.
Pin name
I/O
CS5#
I
A7
I
A6
I
A5
I
A4
I
A3
I
A2
I
A1
I
A0
I
D7
I/O
D6
I/O
D5
I/O
D4
I/O
D3
I/O
D2
I/O
D1
I/O
D0
I/O
RESET#
I
WR#
I
RD#
I
16.6667MHz
I
SOUT1
O
SIN1
I
DSR1
I
DTR1
O
CTS1
I
RTS1
O
DCD1
I
RI1
I
SOUT2
O
SIN2
I
DSR2
I
DTR2
O
CTS2
I
RTS2
O
DCD2
I
RI2
I
SOUT3
O
SIN3
I
DSR3
I
DTR3
O
CTS3
I
RTS3
O
DCD3
I
RI3
I
SOUT4
O
SIN4
I
DSR4
I
DTR4
O
CTS4
I
RTS4
O
DCD4
I
RI4
I
SOUT5
O
SIN5
I
DSR5
I
DTR5
O
CTS5
I
RTS5
O
DCD5
I
RI5
I
MCRINT#
O
MCRINT
O
RDD1
I
RCP1
I
CLS1
I
RDD2
I
RCP2
I
CLS2
I
RDD3
I
RCP3
I
CLS3
I
RCVDT1#
I
RCVDT2#
I
RCVDT3#
I
RCVDT4#
I
RCVDT5#
I
EXINT1#
I
EXINT2#
I
EXINT3#
I
EXINT4#
I
FIRQ#
O
GPIO1
I/O
GPIO2
I/O
GPIO3
I/O
GPIO4
I/O
GPIO5
I/O
GPIO6
I/O
GPIO7
I/O
GPIO8
I/O
GPIO9
I/O
GPIO10
I/O
GPIO11
I/O
GPIO12
I/O
GPIO13
I/O
GPIO14
I/O
No.
Pin name
I/O
GPIO15
I/O
GPIO16
I/O
GPIO17
I/O
GPIO18
I/O
GPIO19
I/O
GPIO20
I/O
GPIO21
I/O
GPIO22
I/O
GPIO23
I/O
GPIO24
I/O
GPIO25
I/O
GPIO26
I/O
GPIO27
I/O
GPIO28
I/O
GPIO29
I/O
GPIO30
I/O
GPIO31
I/O
GPIO32
I/O
118
FPGA_A0
I
No.
Pin name
I/O
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 8
(2) CKDC (Clock, Key, Rear display, Clerk)
The control method of the key, the rear display, and the clerk is the same as that of the UP-600/700.
The CKDC is the new - type CKDC compatible with the old - type CKDC of Hitachi. (For some, the command of Not Used is omitted.)
(3) EFT
It is provided with the UP-104EF compatible with the ER-03EF.
The command system is perfectly compatible with the UP-104EF.
The command system is perfectly compatible with the UP-104EF.
When the UP-I04EF is installed, CH! Of the RS232C is used only for the
EFT.
■ Register composition
Caution: Data write to DTR is allowed when “CLM : 1/IBF : 0”.
Data read from DTR is allowed when “OBF : 1”.
(4) Printer
For details, refer to the predications of the LT1320CS.
■ Related CPU ports
■ Related FPGA ports
CK D C X
SC K
HTS
ST H
KRQ #
SHEN #
STOP #
SRES #
PO 0 - 3
CP U
PT B7
PT B5
RESE T#
Keyboard
Rea r display
LED 7 seg. 7 digits
SCIF1_TXD
SCIF1_CLK
SCIF1_RXD
IRL0#
Inverter
(Lightcontrol)
(Lightcontrol)
Contact-less clerk
DONE (FPGA)
Address
Name
H’1440000E DTR
(Data register)
Used for data send/receive with the
EFT I/F CPU.
EFT I/F CPU.
When WRITE
When READ
When READ
: Machine
3 EFT
: EFT
3 Machine
READ/WRITE may be performed only
when the Caution are satisfied.
when the Caution are satisfied.
H’1440000F
STR
(Status register)
(Status register)
Used for data send/receive with the
EFT I/F CPU.
EFT I/F CPU.
D7 D6 D5 D4 D3 D2 D1 D0
䌘
䌘
䌘
䌘
䌘 CLM
IBF
OBF
䌘 䋺 Not determined
Data to HOST CPU
1
1
䋺 Yes 0䋺 No
Data to SUB CPU
1
1
䋺 Yes 0䋺 No
SUB CPU data read
1
1
䋺 Not reading
0
䋺 Reading
CPU pin
I/O
Signal name / Description
SCIF0_CLK
O
PCLK (PRINTER CLOCK)
SCIF0_TXD
O
PSO (PRINTER DATA)
UCLK (PTH2)
O
PLATCH#
AN1
I
VPRNT : Printer voltage
(The A/D value is 1/10 of the voltage.)
(The A/D value is 1/10 of the voltage.)
AN0
I
HTEMP : Head temperature
(For the constant B, refer to the printer specifica-
tions.)
(For the constant B, refer to the printer specifica-
tions.)
FPGA pin
I/O
Signal name / Description
GPIO1
O
JAS/MSTEP1 (PRINTER MOTOR drive signal)
GPIO2
O
JDS/MSTEP2 (PRINTER MOTOR drive signal)
GPIO3
O
RAS/MSTEP3 (PRINTER MOTOR drive signal)
GPIO4
O
RDS/MSTEP4 (PRINTER MOTOR drive signal)
GPIO5
O
JMOTOFF (PRINTER MOTOR OFF 1)
GPIO7
O
JMOTCUP (PRINTER MOTOR CURRENT UP)
GPIO9
I
JPES# (JOURNAL PAPER END SENDOR)
GPIO11
I
PHUPS (PRINTER HEAD UP)
GPIO12
I
ACUTSW (AUTO CUTTER SW)
GPIO17
O
VHCOM (The printer power ON at H)
GPIO18
O
STRB1#
GPIO19
O
STRB2#
GPIO20
O
STRB3#
GPIO21
O
STRB4#
GPIO22
O
ACUT1
GPIO23
O
ACUT2
GPIO26
O
PRINTER SENSOR ON
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