Sharp UP-800 (serv.man19) Service Manual ▷ View online
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 1
CHAPTER 6. HARDWARE DESCRIPTION
1. BLOCK DIAGRAM
CPU clock
㧦 200MHz
Bus clock
㧦 33MHz
Peripheral clock
㧦 16.6667MHz
Bus endian setting 㧦 Little endian
Controller
Synchronization type serial
Synchronization type
serial
serial
Synchronization type serial
Synchronization type serial
Async type serial
Bus connect
Rear display
Interface
Contactless clerk
Contactless clerk key
Ethernet Controller
etc.
Key
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 2
2. MAJOR DEVICES
3. MEMORY MAP
3-1. NORMAL OPERATION
3-2. WHEN IPL
CPU
Renesas SH7760 (HD6417760BL200A)
256PIN BGA
256PIN BGA
SDRAM
8MB (64Mbit) SAMSUNG K6S643232H-TC/
L70 (
L70 (
×
32) - 32bit connection
FLASH
memory
memory
4MB (32Mbit) SPANSION S29GL032A90TFIR4
(MIRRORBIT)
48pin bottom (00 side) boot
(MIRRORBIT)
48pin bottom (00 side) boot
...
16bit connection
SRAM
2MB (16Mbit) 16bit connection (8bit access enable)
CYPRESS CY62167DV30
CYPRESS CY62167DV30
Expansion
SRAM
SRAM
4MB (32Mbit) 48PIN TSOPI 16Mbit
×
2pcs.
8bit connection
×
2 = 16bit connection
CYPRESS CY62127DV30
LCDC
SH7760 built-in LCD controller
LAN
CONTROLLER
CONTROLLER
10/100base-T Smsc LAN9118 Rev.C
ASIC (FPGA)
XILINX XC3S250E 208PIN
8251
8251
×
3 16450
×
6 Software interrupt,
built-in timer
LCD
LG PHILIPS LB065WQ3
Touch panel
Fujitsu 4-wire type, 6.5inch custom
Touch panel
controller
controller
Asahi Kasei AK4182A
Clock/Key/
Rear display
controller
Rear display
controller
Newly developed controller conforming to Old
Hitachi series CKDC
Hitachi series CKDC
Printer
PR-58HA
Area
Bus
width
Physical space
Space name
Area 0 16bit
H’0000 0000 - H’003F FFFF
Flash memory
area 4MB
area 4MB
H’0040 0000 - H’007F FFFF
EPROM 4MB
H’0080 0000 - H’00BF FFFF
NC (Open)
H’00C0 0000 - H’03FF FFFF
Area 1 16bit/
8bit
H’0400 0000 - H07BFF FFFF
NC (Open)
H07C00 0000
H07E00 0000
H07E00 0000
H’07FF FFFF
SRAM 2MB
Area 2 16bit/
8bit
H’0800 0000 - H’083F FFFF
Expansion
SRAM area 4MB
SRAM area 4MB
H’0840 0000 - H’087F FFFF
NC (Open)
H’0880 0000 - H’0BFF FFFF
Area 3 32bit/
16bit/
8bit
H’0C00 0000 - H’0C7F FFFF SDRAM area 8MB
H’0C80 0000 - H’0FFF FFFF
NC (Open)
Area 4 16bit
H’1000 0000 - H’1000 00FC
LAN controller
H’1000 00FD - H’13FF FFFF
NC (Open)
Area 5 8bit
H’1400 0000 - H’17FF FFFF
FPGA
EFT
Area 6 16bit
H’1800 0000 - H’181F FFFF
NC (Open)
H’1820 0000 - H’183F FFFF
H’1840 0000 - H’1BFFFFFF
Area 7
H’1C000000 - H’1FFFFFFF
Reserved
Area
Bus
width
Physical space
Space name
Area 0 16bit
H’0000 0000 - H’003F FFFF
EPROM 4MB
H’0040 0000 - H’007F FFFF
Flash memory
area 14MB
area 14MB
H’0080 0000 - H’00BF FFFF
NC (Open)
H’00C0 0000 - H’03FF FFFF
Area 1 16bit/
8bit
H’0400 0000 - H07BFF FFFF
NC (Open)
H07C00 0000
H07E00 0000
H07E00 0000
H’07FF FFFF
SRAM 2MB
Area 2 16bit/
8bit
H’0800 0000 - H’083F FFFF
Expansion
SRAM area 4MB
SRAM area 4MB
H’0840 0000 - H’087F FFFF
NC (Open)
H’0880 0000 - H’0BFF FFFF
Area 3 32bit/
16bit/
8bit
H’0C00 0000 - H’0C7F FFFF
SDRAM area 8MB
H’0C80 0000 - H’0FFF FFFF
NC (Open)
Area 4 16bit
H’1000 0000 - H’1000 00FC
LAN controller
H’1000 00FD - H’13FF FFFF
NC (Open)
Area 5 8bit
H’1400 0000 - H’17FF FFFF
FPGA
EFT
Area 6 16bit
H’1800 0000 - H’181F FFFF
NC (Open)
H’1820 0000 - H’183F FFFF
H’1840 0000 - H’1BFFFFFF
Area 7
H’1C000000 - H’1FFFFFFF
Reserved
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 3
4. BUS
D15
-0
CPU
SDRAM
D31- 0
D31-0
D31- 0
D15
-0
SRAM
SRAM
16Mbit
1
SRAM
SRAM
16Mbit
2
FLASH
D15
-0
ENABLE
RD#
ENABLE
D15
-0
FPGA
LANC
ADDRESS
A14
-2
A10
-0
BA1, BA0,
SUB PWB
φ Direction ENABLE
A22
-1
DONE
A22
-1
D15/A-1
A0
2.5V
ψ3.3V
A0
A21-
0
D14
-
0
(Expansion)
Except for the area
SDRAM
Bidirectionalb
uff
er
Buffer
Connector
UP-820N/820F (V)
HARDWARE DESCRIPTION
6 – 4
5. CONNECTION DEVICE
5-1. SDRAM (CPU PWB)
8MB (64Mbit) SAMSUNG K6S643232H-TC/L70 (
×
32)
Used in 32bit connection.
5-2. FLASH ROM (CPU PWB) /EPROM
(SUB PWB : QA0 ONLY)
(1) FLASH ROM
4MB (32Mbit) SPANSION S29GL032A90TFIR4 (MIRRORBIT 000000h
side boot sector) is used. The jumper pin and the socket are used to
side boot sector) is used. The jumper pin and the socket are used to
switch the FLASH memory (4MB) and the EPROM (1MB
×
4).
<When IPL>
When the signal (IPL#) from the jumper pin is 1, the FLASH memory is
assigned to the space of H’0000 0000 -H’003F FFFF. When the signal
(IPL#) from the jumper pin is 0, the FLASH memory is assigned to the
space of H’0040 0000-H’007F FFFF.
space of H’0040 0000-H’007F FFFF.
■ Connection
(2) EPROM
The EPROM PWB is installed to the connector for the UP-I04EF.
5-3. SRAM
2MB (16Mbit) 48PIN TSOPI 16Mbit
×
1 pc. 16bit connection
6bit & 8bit access enabled. Backup is enabled by a battery.
■ External decoder
*When the power is turned OFF, CS1 - 1# and CS1 - 2# are non-active.
■ SRAM connection
5-4. EXPANSION SRAM
4MB (32Mbit) 48PIN TSOPI 16Mbit
×
2 pcs. 8bit connection
×
2 = 16bit
connection CYPRESS CY62127DV30
16bit & 8bit access enabled. Backup is enabled by a battery.
■ External decoder
*When the power is turned OFF, CS2-1# and CS2-2# are non-active.
■ SRAM connection
CPU
SDRAM
CKIO
CLK
CS3#
CS#
CKE
CKE
A12 - A2
A10 - A0
A14
BA1
A13
BA0
RAS#
RAS#
RD/CASS/FRAME
CAS#
RD/WR#
WE#
WE3/DQM3/ICIOWR
DQM3
WE2/DQM2/ICIORD
DQM2
WE1/DQM1
DQM1
WE0/DQM0/REG
DQM0
D31 - D0
DQ31 - 0
CPU
External signal
FLASH
A21 - A1
1
A20 - A0
CS0#, IPL#
FCS#
CE#
RD#
1
OE#
WE1#
1
WE#
D15 - D0
1
D15 - D0
CAN1_TX/AUDATA [1]
PTA2_RYBY#
RY/BY#
PULLUP
WP#
RESET#
RESET#
BYTE#
BYTE#
CPU
EPROM1
EPROM2
EPROM3
EPROM4
A20 - A1
A19 - A0
A19 - A0
A19 - A0
A19 - A0
CS0#, A21,
IPL#
External
signal :
PCS1# (E#)
External
signal :
PCS1# (E#)
External
signal :
PCS2# (E#)
External
signal :
PCS2# (E#)
RD#
G#
G#
G#
G#
D15 - D8
—
D7 - D0
—
D7 - D0
D7 - D0
D7 - D0
—
D7 - D0
—
CS1#
0
1
A21
0
CS1 - 1# Active
—
1
CS1 - 2# Active
—
CPU
SRAM1
A20 - A1
A19 - A0
CS1#, A21
CS1 - 1#
RD#
OE#
WE1#
—
WE0#
WE#
D15 - D0
D15 - D0
CS2#
0
1
A22
0
CS2-1# Active
—
1
CS2-2# Active
—
CPU
SRAM1
SRAM2
A21 - A1
A20 - A0
A20 - A0
CS2#, A22
CS2 - 1#
CS2 - 1#
RD#
OE#
OE#
WE1#
—
WE#
WE0#
WE#
—
D15 - D8
—
D7 - D0
D7 - D0
D7 - D0
—
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