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4

OPC1 pin table

The signals marked with "-" at the end are LOW active signals. Example: "CS1-" = "CS1"

No.

Pin No.

Pin name

I/O

Pin

ER-A610

Description

1

80

SL00

I

ICU

GND

RS-232/UNIT0 channel select

2

79

SL01

I

ICU

GND

3

78

SL02

I

ICU

GND

4

77

SL10

I

ICU

GND

RS-232/UNIT1 channel select

5

76

SL11

I

ICU

GND

6

75

SL12

I

ICU

GND

7

95

SL20

I

ICU

GND

RS-232/UNIT2 channel select

8

96

SL21

I

ICU

GND

9

52

SL22

I

ICU

GND

10

54

SL30

I

ICU

+5V

RS-232/UNIT3 channel select

11

93

SL31

I

ICU

GND

12

94

SL32

I

ICU

GND

13

36

CS0-

O

O

NC

RS-232 USART chip select

14

32

CS1-

O

O

NC

15

2

CS2-

O

O

CS3-

16

1

CS3-

O

O

NC

RS-232/INLINE USART chip select

17

81

CD0-

I

IS

+5V

RS-232 control signal CD- input

18

46

CD1-

I

IS

+5V

19

88

CD2-

I

IS

+5V

20

38

CD3-/P0-

I

IS

CD3-/PO-

RS-232 CD-/INLINE P0-

21

82

CTS0-

I

IS

+5V

RS-232 control signal CTS- input

22

47

CTS1-

I

IS

+5V

23

86

CTS2-

I

IS

+5V

24

43

CTS3-/P1-

I

IS

CTS3-/P1-

RS-232 CTS-/INLINE P1-

25

48

CI0-

I

IS

+5V

RS-232 control signal CI- input

26

45

CI1-

I

IS

+5V

27

87

CI2-

I

IS

+5V

28

99

CI3-/P2I

I

IS

CI3-/P21

RS-232 CI-/INLINE P2I

29

55

BRK0

I

ISC

GND

RS-232 USART BREAK signal

30

70

BRK1

I

ISC

GND

31

27

POFF-

I

IS

POFF-

POFF signal (LOW: P-OFF, HIGH: P-ON)

32

4

BRK3

I

IS

BRK3

RS-232/INLINE USART BREAK signal

33

57

RCVRDY0

I

ISC

GND

RS-232 USART RCVRDY signal

34

72

RCVRDY1

I

ISC

GND

35

74

RCVRDY2

I

ISC

GND

36

6

RCVRDY3

I

IS

RCVRDY3

RS-232/INLINE USART RCVRDY signal

37

59

TRNRDY0

I

ISC

GND

RS-232 USART TRNRDY signal

38

71

TRNRDY1

I

ISC

GND

39

98

TRNRDY2

I

ISC

GND

40

5

TRNRDY3

I

IS

TRNRDY3

RS-232/INLINE USART TRNRDY signal

41

56

TRNEMP0

I

ISC

GND

RS-232 USART TRNEMP signal

42

60

TRNEMP1

I

ISC

GND

43

100

TRNEMP2

I

ISC

GND

44

3

TRNEMP3

I

IS

TRNEMP3

RS-232/INLINE USART TRNEMP signal

45

58

RCVDT0

I

ISC

+5V

RS-232 RCVDT signal (LOW: TIMER START)

46

73

RCVDT1

I

ISC

+5V

47

97

RCVDT2

I

ISC

+5V

48

41

RCVDT3

I

IS

RCVDT3

RS-232/INLINE RCVDT signal

49

20

RSRQ-

O

3S

RSRQ-

RS-232 IRQ- signal

50

83

TRV-

I

ISC

+5V

INLINE YES/NO

51

7

RXDATA0

O

O

NC

INLINE RXDATA OUT

52

42

TXE

O

O

NC

INLINE TRNS ENABLE

53

84

TRRQ-

O

3S

NC

INLINE IRQ- signal

54

28

TRQ1-

O

3S

TRQ1

TIMER IRQ signal (RS-232)

 32 

No.

Pin No.

Pin name

I/O

Pin

ER-A610

Description

55

29

TRQ2-

O

3S

NC

TIMER IRQ signal (INLINE)

56

11

D0

I/O

IOU

D0

DATA BUS (MAIN)

57

12

D1

I/O

IOU

D1

58

13

D2

I/O

IOU

D2

59

14

D3

I/O

IOU

D3

60

16

D4

I/O

IOU

D4

61

17

D5

I/O

IOU

D5

62

18

D6

I/O

IOU

D6

63

19

D7

I/O

IOU

D7

64

61

DB0

I/O

IOU

DB0

DATA BUS (USART)

65

62

DB1

I/O

IOU

DB1

66

63

DB2

I/O

IOU

DB2

67

64

DB3

I/O

IOU

DB3

68

66

DB4

I/O

IOU

DB4

69

67

DB5

I/O

IOU

DB5

70

68

DB6

I/O

IOU

DB6

71

69

DB7

I/O

IOU

DB7

72

21

A0

I

I

A0

ADDRESS BUS (MAIN)

73

22

A1

I

I

A1

74

23

A2

I

I

A2

75

24

A3

I

I

A3

76

25

A4

I

I

A4

77

26

A5

I

I

A5

78

10

OPTCS-

I

I

OPTCS-

OPTION CHIP SELECT (from MAIN)

79

31

RDO-

I

I

RDO-

READ signal (from MAIN)

80

30

WRO-

I

I

WRO-

WRITE signal (from MAIN)

81

9

RES-

I

IS

RES-

RESET signal (from MAIN)

82

34

R-

O

O

R-

READ signal (To USART)

83

37

W-

O

O

W-

WRITE signal (To USART)

84

51

RES

O

O

RES

RESET signal (To USART)

85

92

X1

O

NC

cillation circuit

86

91

X2

I

X2

87

53

XOUT

O

O

XOUT

Clock for USART 

88

8

TRCK

O

O

TRCK

T/R clock for 1CH USART

89

35

AB0

O

O

AB0

Address bus for USART

90

33

AB1

O

O

NC

91

85

USICH

I

ISC

+5V

UNIT3 USART 1CH/2CH select

92

50

PX

O

NC

Power source clock

93

39

VCC

+5V

94

89

VCC

+5V

95

15

GND

GND

96

40

GND

GND

97

65

GND

GND

98

90

GND

GND

99

49

RTS0-

O

O

NC

RS-232 control signal RTS- output

100

44

RTS1-

O

O

NC

ICU : CMOS level input (internal pullup resistor)
O

: Output

IS

: TTL level input (internal schmit circuit)

ISC : CMOS level input (internal schmit circuit)
3S

: Three state output

IOU : I/O port (internal pullup resistor)

 33 

The 7051G is a Universal Synchronous/Asynchronous Receiver/
Transmitter (USART) Chip designed for data communications in mi-
crocomputer systems. The USART is used as a  peripheral device
and is programmed by the CPU to operate using virtually any serial
data transmission technique presently in use. The USART accepts
data characters from the CPU in parallel format and then converts
them into a continuous serial data stream for transmission. Simulta-
neously it can receive a serial data stream and convert them into
parallel data characters for the CPU. The USART will signal the CPU
whenever it has received a character for the CPU. The CPU can read
the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNC/BRK, TxEMPT.

NC

33

1 

PIN  CONFIGURATION

NC

32

WR

31

TxCLK

30

D7

29

NC

28

D6

27

D5

26

D4

25

NC

24

NC

23

NC

12

Rx

CL

K

13

VD

D

14

D0

15

D1

16

IC

17

D2

18

D3

19

Rx

DA

T

A

20

GN

D

21

NC

22

NC

1

NC

2

TxDATA

3

CLK

4

RESET

5

NC

6

DSR

7

RTS

8

DTR

9

NC

10

SYNC/BRK

11

NC

44

Tx

E

M

P

43

CT

S

42

S

Y

NC/

B

R

K

41

T

x

RDY

40

NC

39

Rx

RDY

38

RD

37

C/

D

36

CS

35

NC

34

µPD71051G

Pin  name

Description

2 

PIN  DESCRIPTION

Data bus (8bits)
Transmitter data
Transmitter clock
Transmitter ready
Transmitter empty
Receiver data
Receiver clock
Receiver ready
Clock pulse
Reset
Data set ready
Request to send data
Data terminal ready
Write data
Chip enable
Control or data is to be written or read
Read data
Break
+5V

D0~D7
TXDATA
TXCLK
TXRDY
TXEMP
RXDATA
RXCLK
RXRDY
CLK
RESET
DSR
RTS
DTR
WR
CS
C/D
RD
SYNC/BRK
VDD

3

 BLOCK  DIAGRAM

D7-D0

RESET

CLK

C/D

RD

WR

CS

DSR
DTR

CTS
RTS

TXDATA

TXRDY

TXEMP

TXCLK

RXDATA

RXRDY

RXCLK

SYNC/BRK

DATA

BUS

BUFFER

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

TRANSMIT

BUFFER

(P.S)

CONTROL

RECEIVE

BUFFER

(S.P)

TRANSMIT

RECEIVE

CONTROL

INTERNAL
DATA  BUS

 34 

1) This diagnostic program has been developed for diagnosing ma-

chine functions in the field. The program is contained with in the
ER-A610.
The diagnostic program is stored in the external ROM which will
be executed by the CPU (H8/510) which requires the following
diagnostic operations:

a) Proper power supply voltages are mandatory for logic circuits

(+5V, VRAM, VCKDC, POFF, 12V, +24V).

b) CPU input/output pins, CPU internal logic, CKDC4, MPCA5,

TPRC, address decoder, address bus, data bus, and common
ROM/RAM must be working properly.

To start the diagnostic program, you must enter the following com-
mand.
3-digit test item number 

→

 TL  key in the SRV mode.

The key assignment must be properly set and a part for ROM and
RAM must be operating properly to go into this mode because the
control jumps to the program area in the SRV mode. A master reset
must be performed before operating the ECR for the first time. After
any option is installed, a program reset is required. When the master
reset or program reset is performed, be sure to check the printout on
the journal paper.

Master reset:

Turn power on in the SRV’ mode and change it
to the SRV mode with the  JF  key pressed.

Journal print:

MASTER RESET ***

Program reset: Turn power on in the SRV’ mode and change it

to the SRV mode.

Journal print:

PRG. RESET ***

With the SRV mode and the following command entry, the test starts.

Code

Description

100

Display test-1

101

Key, clerk, and switch position code display

102

R/J printer test

103

Slip printer test

104

Keyboard test

105

Mode switch test

106

Validation sensor and near end sensor test

107

BOF, TOF and IFV test

108

Calendar oscillator test

109

SSP test

110

Drawer-1 open and sensor test

111

Drawer-2 open and sensor test

112

Drawer-3 open and sensor test

113

Drawer-4 open and sensor test

116

Display test-2

117

SIO test-1

120

Standard RAM test

130

Standard ROM test

150

R/J printer dot pulse width adjustment

200

(

206

Option RAM chip test

300

(

306

Option RAM address test

400

Option ROM test

1

Key operation

100 

→

 TL 

2

Functional description
The following is displayed:

3

Check the following items:

a) Check for proper activation of display elements.

b) Check for blur, uneven illumination, and partial omission.

4

Test termination
Press any key. The test terminates with the test and message
printed.

                        100

Test termination print

1

Key operation

101 

→

 TL 

2

Functional description
Key, clerk, and receipt switch codes are displayed.

3

Check the following items:
Change key and switch positions for proper display activation.

Clerk code:

Stay down key

000 (off state)
001 (Clerk A)
002 (Clerk B)
004 (Clerk D)
008 (Clerk E)

Receipt switch code:   0 (on state) 1 (off state)
Key code:

--- (simultaneous two key)
   depression, invalid entry)
   001 ~ 126

NOTE: Refer to JOB#104, key soft code, for the key code. (Fig.

3-2.)

4

Test termination
Change the MODE switch position other than SRV position to
terminate the test. The test termination message is printed.

                        101

Test termination print

DOT DISPLAY :

C L

S W

K

Key code

Receipt SW code

Clerk code

POP-UP DISPLAY:

DOT DISPLAY

:

 35 