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Model
ER-A610 (serv.man4)
Pages
64
Size
1.03 MB
Type
PDF
Document
Service Manual
Brand
Device
ECR / ERA610 Service Manual
File
er-a610-sm4.pdf
Date

Sharp ER-A610 (serv.man4) Service Manual ▷ View online

<Dot display>
Fig. 9-6
IMPORTANT:
The CKDCIII lines are not high voltage resistive ports. Damage may
occur to the CKDC4 if lines are ahorted carelessly when using oscillo-
scope probes.
Dot matrix tube
A 4-bit binary output signals (ST0-ST3) from CDKC4 are converted
into the digit drive signal (DG0-DG15) in the M66004FP. 
<Dot display control>
The CKDC4 controls the character segment (5 x 7) and the indicator
of the dot display by using the controller (M66004FP) for dot display
control.
1
M66004PF/Dot display control signal
Signal
name
Contents
Pin/Remark
DSO
Serial data output signal
for M66004FP
C-MOS pin
DSCK
Serial shift clock output
signal for M66004FP
C-MOS pin. 
Requires to be pulled up
DCS
Chip select output signal
for M66004FP
C-MOS pin
10. Power supply circuit
Fig. 10-1
+24V:
Printer, solenoid power
+5V:
VCC (Logic power)
+12V:
Battery charge, IN-LINE driver power
–32V:
Display tube power
VF1, VF2:
Display tube power (AC)
VRAM:
Battery back-uped power
VCKDC:
CKDC III Back-up power
For the DC-DC converter, refer to section 8 of cash register Basic
manual.
11. Switching regulator circuit
Fig. 11-1
By switching VIN (+28.8V) by the transistor TR1 within the STR2124,
DC+24V supply is obtained through the LC network. Stable +24V is
obtained by controlling on/off duty of TR1.
ION:
Current when TR1 is on.
IOFF: Current when TR1 is off.
ENST
ST0~ST3
19.1µ s
DGn
"h" th digit
display
DGn+1
Display off
D11~D75
"h" th didit display pattern
(h+1) th didit display pattern
17.2µ s
(h+1) th digit display
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
Noise filter
Switching
regulator
DC-DC
Converter
circuit
Battery
circuit
VRAMP
+5V
+12V
-32V
VF1/VF2
F1
F2
Switching
regulator
(STR2124)
+24V
+
-
~
~
VCKDC
VIN
+28.8V
+
6800µ
63V
5
VIN
TR 1
Refer-
ence
voltage
circuit
3
2
4
1
L1 220µ H
IOFF
ION
+24V
Load
C 2
2200µ F
35V
R2
VR1
 28 
12. Scanner interface
The ER-A610 includes the RS-232 interface which has the power
supply function to the hand scanner (ER-A6HS1) as a standard provi-
sion.
1) Block diagram
When the ER-A6HS1 is connected, +5V power is supplied to Pin 9 of
the RS-232 connector.
SW1 on the RS-232 interface allows switching of the VS signal (+5V)
and the CI signal.
SYNC/BRK
TXRDT,RXRDT,TXEMPT
OPC1
F256004
CLK
REST
DB0~DB7
RD,WR
CS
C/D
DSR1
USART
µPD-
71051
DTR1,TXDATA,RTS1
DCD,CTS1
RXDATA
CI1
Receiver
Driver
MAX211
CD,CS
RD
DR
ER,SD,RS
1
CD
2
DR
3
RD
4
RS
5
SD
6
CS
7
ER
8
CI
9
VS
10
GND
+5V
1
CD
2
RD
3
SD
4
ER
5
GND
6
DR
7
RS
8
CS
9
VS/CI
DSUB-9pin
SW1
SW1
CI
+5V
+5V output
When connecting with ER-A6HS1
CI signal output
DSCN
RSCN
ER-A6HS1
Main PWB
RS232C I/F
CI
 29 
2) Description of main LSI
2)-1. OPC1 (F256004PJ)
1
 General description
The OPC1 is a gate array of integrated peripheral circuits of RS-
232/Simple IRC interface. 
One chip of the OPC1 is equipped with four communication circuits.
(Three of them are for RS-232 only: UNIT 0 ~ 2, one is for selection
of simple IRC/RS-232: UNIT 3)
The ER-A610 uses UNIT3 (RS-232 interface).
UNIT NO.
Purpose
ER-A610
UNIT0
RS-232
Not used.
UNIT1
RS-232
Not used.
UNIT2
RS-232
Not used.
UNIT3
RS-232/Simple IRC
Used.
Each UNIT of the OPC1 has the following functions:
1
Timer function 
Used for the timer between characters in data reception. 
2
Address decode
USART chip select output and own select.
3
Interruption control
RSRQ,  TRRQ output using outputs from USART (TRNRDY,
TRNEMP, RCVRDY, BRK) and RS-232 control signals (CI, CTS,
CD) as interruption factors.
(For the simple IRC, TRNEMP is excluded.)
RSRQ:
TRRQ(Not used):
For RS-232 
For simple IRC
4
Simple IRC send/receive control (UNIT3 only) : Not used
2
 Pin configuration
CS3
CS2
TRNEMP3
BRK3
TRANDY3
RCVRDY3
RXDATA0
TRCK
RES
OPTCS
D0
D1
D2
D3
GND
D4
D5
D6
D7
RSRQ
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
T
RNE
M
P
2
CI
3/
P
2
I
T
RNRDY
2
RCV
DT
2
SL
2
1
SL
2
0
SL
3
2
SL
3
1
X1
X2
GN
D
VC
C
CD2
CI
2
CT
S
2
US
IC
H
T
RRQ
TR
V
CT
S
0
CD0
SL
0
0
SL
0
1
SL
0
2
SL
1
0
SL
1
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A5
PO
F
F
TR
Q
1
WR
O
RD
O
CS
1
AB
1
R
AB
0
CS
0
W
CD3
/P
0
VC
C
GN
D
RCV
DT
3
TX
E
CT
S
3
/P
1
RT
S
1
CI
1
CD1
CT
S
1
CI
0
RT
S
0
PX
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SL12
RCVRDY2
RCVDT1
RCVRDY1
TRNRDY1
BRK1
DB7
DB6
DB5
DB4
GND
DB3
DB2
DB1
DB0
TRNEMP1
TRNRDY0
RCVDT0
RCVRDY0
TRNEMP0
BRK0
SL30
XOUT
SL22
RES
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OPC1
F256004PJ
TR
Q
2
 30 
3
 Block diagram
D7
D6
D5
D4
D3
D2
D1
D0
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Data bus buffer
WRO
RDO
RES
W
R
RES
Read/write
control
A5
A4
A3
A2
A1
A0
SL00
CS0
Decorder
control
SL01
SL02
SL10
SL11
SL12
SL20
SL21
SL22
SL30
SL31
SL32
TRV
USICH
CS3
CS2
CS1
C
hanel
 s
e
le
c
t c
ont
ro
l
CHSL
PX
TO/FROM USART
RX
DA
T
A
0
TX
E
X1
X2
XO
U
T
TB
C
K
Inline
cont
OCS
TCR0
Timer0 control
Timer0
RCVDT0
TCR1
Timer1 control
Timer1
RCVDT1
TCR2
Timer2 control
Timer2
RCVDT2
TCR3
Timer3 control
Timer3
RCVDT3
RTS CNT
RTS1
RTS0
PO
F
F
RS
RQ
T
RRQ
TR
Q
1
TR
Q
2
Power
supply
cont.
RCVRDY3
RCVRDY2
RCVRDY1
RCVRDY0
TRNEMP3
TRNEMP2
TRNEMP1
TRNEMP0
Interrupt control
CI
0
CI
1
CI
2
CI
3
/P
2
I
CD0
CD1
CD2
CD3
/P
0
CT
S
0
CT
S
1
CT
S
2
CT
S
3
/P
1
BR
K0
BR
K1
BR
K3
T
R
NRD
Y
0
T
RNRDY
1
T
RNRDY
2
T
RNRDY
3
AB1
AB0
 31 
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