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(

∗

1)  “Internal I/O” means the registers in the H8/510.

(

∗

2)  “External I/O” means the base system I/O area to be ad-

dressed in page 0. 

(

∗

3)

"Memory image area" means the lower 32KB of ROM area
which is projected to 000000H ~ 007FFFH for allowing reset
start and other vector addressing, or the lower 32KB of ROM
area which is projected to 008000H ~ 00FE7FH for allowing 0
page addressing of work RAM area. 

(

∗

4)  “Expansion I/O” means expansion I/O device area which isad-

dressed to area other than page 0.

2

Fig. 5-2

•

ROM image area: Image is formed in ROM area address C00000H
C07FFFH. This area is identical to IPL ROM area which will be-
separately developed. 

•

RAM image area: Image is formed in RAM area address
1D8000H1DFE7FH. (

∗

Note)  

∗

Note:  Image can be formed in lower 32KB of RAS2.

3

Fig. 5-3

These two decode signals decode 512KB space respectively and
canbe used with max. 4MB ROM. 

∗

Note: The lower 32KB of ROS1 signal is formed as OR of

image area in 0page. 

4

Fig. 5-4

In the three RAM chip select, the following address is decoded. 

000000H

004000H

008000H

00FFFFH

1FFFFFH

ROM image area
32KB

RAM image area
slightly smaller than32KB

NOT USE

00F800H

00FE80H

00FF80H

00FFFFH

RAM image area

Internal I/O area

External I/O area
(0 page)

1BFFFFH

RAM area

100000H

400000H

BFFFFFH

NOT USE

NOT USE

RAS1  128KB

RAS2  128KB

RAS3
1MB
(2MB)

1C0000H

1E0000H

200000H

100000H

400000H

BFFFFFH

NOT USE

NOT USE

RAS1  128KB

RAS2  128KB

RAS3
1MB
(2MB)

1C0000H

1E0000H

200000H

 20 

CS signal

Address

•

 RAS1

1C0000H~1DFFFFH
(008000H~00FE7FH) 

∗

 Note

•

 RAS2

1E0000H~1FFFFFH
(008000H~00FE7FH) 

∗

 Note

•

 RAS3

200000H~3FFFFFH

∗

Base signal is for 2M. 

∗

Note:  RAS1 signal is formed as OR in the image area of 0 page.j

(Lower 32KB). 
RAS2 signal is formed as OR in the image area of 0 page.
(lower32KB).

5

Fig. 5-5

∗

Note 1: MPCCS signal is the base signal for MPCA5 internal reg-

isterdecoding, and does not exist as an internal signal.

∗

Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC

(optionperipheral controller) using the base signal OPTCS
for optiondecoding. They does not exist as external sig-
nals.

Fig. 5-6

1

Fig. 5-7

IPLON:  IPL board detection signal incorporated in the option slot.

Note used in the ER-A650. (Not used)

Access is performed with two ROM chip select signals ROS1 and
ROS2, which decode 512KB address area respectively to access-
max. 4MB ROM. 

2

Fig. 5-8

Access is performed with two RAM chip select signals RAS1, RAS2
and RAS3. The control register in MPCA5 allows selection of  page-
image memory area. (RAS1 is selected for initializing.)

∗

: For 0 page image area, selection between RAS1 and RAS2 can

bemade with the control register. The 0 page control registerper-
forms initializing at the timing of no stack processimmediately
after resetting. 

This is the circuit employed to do the Special Service Preset(SSP). 

(Block diagram)

Fig. 6-1

00FF80H

00FFA0H

00FFFFH

MPCCS

NOT USE

NOT USE

NOT USE

NOT USE

OPCCS1

OPCCS2

00FFC0H

00FFD0H

00FFE0H

00FFF0H

(*1)

(*2)

(*2)

CPU

MPCA5

ROM1

RAM1

RAM2

(OPTION)

ROM2

(OPTION)

RAM3: Memory PWB

(OPTION)

Data bus

Address bus

ROS1

ROS2

RAS1

RAS3

RAS2

Address

A23~A14

(IPLON)

Address

decorder

C80000H~CFFFFFH

C00000H~C7FFFFH

000000H~007FFFH

MPCA5

ROS2

ROS1

Address

A23~A14

Address

decorder

1C0000H~1DFFFFH

008000H

~

00F7FFH

*1

1E0000H~1FFFFFH

RAS1

RAS2

RESET

D

CK

Q

R

DOI

S8F

Control register

MPCA5

CPU

MPCA5

A0~23

D0~D7

NMI

SSPRQ

 21 

(MPCA5 block diagram)

Fig. 6-2

As the address detection system, the brake address register compari-
son system is employed though the mapping system was employed
in the conventional monitor RAM. The address registerlocated in
MPCA is always compared with the system address bus to monitor
and generate NMI signal at a synchronized timing and togo to NMI
exception process. 
In the exception process routine service routine, the entry address is
checked to go to SSP sub routine. 
Entry to the break address register (BAR) is performed through ad-
dress FFFF00H or later decoded in MPCA5. 

The break address register (BAR) is accessed through direct address
of FFFF00H~FFFFFFH. Entry number is 32 entry.

Fig. 6-3

D0~

    D7

A23~

     A0

BAR  0

BAR  N

REGCS

Decode

Comparator

Coincide

Coincide

SPE

(Enable register)

SSPRQ

(NMI)

Control signal

ROMCS

O

N

1

2

3

4

FFFF00

H

1

2

3

4

5

6

7

BAR0

BAR1

BAR2

7

0

 22 

Each BAR is composed of 4 byte address. Bit composition is as
follows:

Fig. 6-4

4

 is the enable register. The entry registers of the break address are

assigned to 

1

, 

2

, and 

3

. Each bit of address corresponds to each

bit position, writing to 

1

, 

2

, and 

3

 is performed without shifting. The

corresponding area is 1MB space of ROS1 and ROS2.  

Access to SSP break address register is performed through the tem-
porary register as shown below:

Fig. 6-5

Enable flags can be accessed individually. 
Though enable register 

4

 can be accessed individually, writing to

brake address registers 

1

 and 

2

 is performed at the same time as

writing to brake address register 

3

 through the temporary register. 

Therefore, set 

1

 and 

2

 to temporary, then write into 

3

 at last. 

Since the temporary register is commonly used by BAR sets, thefol-
lowing register setting is performed after completion ofsetting of each
break address register. 

3

Access to the enable register and the brake address register is only
possible when writing to them from the CPU. 

Information on which brake register the SSP brake is detected in is
read as binary data by reading address FFFFFFH (*1). 
Used in an expanded register. 
Normally is a reserve bit. Whenreading, fixed to 0.

If there are 32 break registers, binary expression is made with the
above 5 bits, and 0th is “00000

B

” and 31st is “11111

B

.” 

When detected simultaneously by two or more break registers,
onewith the smaller BAR number is read as binary data. 

The brake signals (NMI) and the above detection data (CMP0~4)
areheld until the above detection data are read. So read should be-
made in the NMI sub routine. (Clear by FFFFFFH read.)

∗

1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). There-

fore,unnecessary read access in parentheses should not be
performed. 

1

2

3

4

A19 A18 A17 A16 A15

A8

A7

A2

EN

Upper bits

Intermediate bits

Lower bits

Enable register

EN (bit7) = 1 Enable
               = 0 Inhibit

Don't care for "-----."

< BAR composition >

1

2

3

4

A19 A18 A17 A16 A15

A8

A7

A2

EN

WR

WR

Temporary

Temporary

bit 7

6

5

4

3

2

1

0

0

0

CMP4

0

CMP3 CMP2 CMP1 CMP0 (FFFFFFH)

 23 