Sharp ER-A450S (serv.man5) Service Manual ▷ View online
Pin
No.
Signal
name
In/Out
Function
130 GND
—
GND
131 GND
—
GND
132 GND
—
GND
133 BA6
O
Address bus 6 for PB-RAM
134 BA5
O
Address bus 5 for PB-RAM
135 BA4
O
Address bus 4 for PB-RAM
136 BA3
O
Address bus 3 for PB-RAM
137 BA2
O
Address bus 2 for PB-RAM
138 BA1
O
Address bus 1 for PB-RAM
139 PHAI
I
TPRC1 clock input pin (9.83 MHz)
140 Vcc
—
+5V
141 Vcc
—
+5V
142 Vcc
—
+5V
143 BA0
O
Address bus 0 for PB-RAM
Pin
No.
Signal
name
In/Out
Function
144 BD7
I/O
Data bus 7 for PB-RAM
145 BD6
I/O
Data bus 6 for PB-RAM
146 BD5
I/O
Data bus 5 for PB-RAM
147 GND
—
GND
148 BD4
I/O
Data bus 4 for PB-RAM
149 BD3
I/O
Data bus 3 for PB-RAM
150 GND
—
GND
151 GND
—
GND
152 GND
—
GND
153 BD2
I/O
Data bus 2 for PB-RAM
154 BD1
I/O
Data bus 1 for PB-RAM
155 BD0
I/O
Data bus 0 for PB-RAM
156 BRAS
O
PB-RAM chip select: Active HIGH (Nu)
157 BRAS
O
PB-RAM chip select: Active LOW
158 RESET
I
TPRC1 reset signal
159 GND
—
GND
160 NU
—
GND
2-5. OPC2
1) Pin configuration
1
SL00
2
SL01
3
SL02
4
SL10
5
SL11
6
SL12
7
SL20
8
SL21
9
SL22
10
SL30
11
SL31
12
13
13
/CD0
14
BRK0
15
TRNEMP0
16
RCVRDY0
17
TRNRDY0
18
/CTS0
19
RCVDT0
20
VCC
21
GND
22
/CI0
23
/RTS0
24
/CS0
25
/CD1
26
BRK1
27
TRNEMP1
28
RCVRDY1
29
TRNRDY1
30
/CTS1
31
32
33
32
33
/RTS1
34
35
36
35
36
TRNEMP2
37
RCVRDY2
38
TRNRDY2
39
CTS2Z
40
RCVDT2
160
MCLK
159
158
RSLCT1
157
RSLCT0
156
/RIN
155
/WIN
154
SYCBKD
153
TRNEMPD
152
RCVRD
YD
151
TRNRD
YD
150
/DSRD
149
/CTSD
148
RCVDTD
147
/R
TSD
146
/DTRD
145
TRNDTD
144
/CSD
143
GND
142
VCC
141
SYCBKC
140
TRNEMPC
139
RCVRD
YC
138
TRNRD
YC
137
/DSRC
136
/CTSC
135
RCVDTC
134
/R
TSC
133
/DTRC
132
TRNDTC
131
/CSC
130
GND
129
SYCBKB
128
TRNEMPB
127
RCVRD
YB
126
TRNRD
YB
125
/DSRB
124
/CTSB
123
RCVDTB
122
/R
TSB
121
/DTRB
41
/CI2
42
/CS2
43
/CD3
44
BRK3
45
TRNEMP3
46
RCVRD
Y3
47
TRNRD
Y3
48
/CTS3
49
RCVDT3
50
/CI3
51
/CS3
52
D0
53
D1
54
D2
55
D3
56
GND
57
D4
58
D5
59
D6
60
D7
61
GND
62
VCC
63
X1
64
X2
65
XOUT
66
TRCK
67
AB0
68
AB1
69
US1CH
70
PX
71
/POF
72
/RSRQ
73
/TR
V
74
RXD
A
T
A
0
75
TXE
76
/TRRQ
77
/TRQ1
78
/TRQ2
79
A0
80
A1
120
TRNDTB
119
/CSB
118
GND
117
SYCBKA
116
TRNEMPA
115
RCVRDYA
114
TRNRDYA
113
/DSRA
112
/CTSA
111
RCVDTA
110
/RTSA
109
/DTRA
108
TRNDTA
107
/CSA
106
UTST
105
DBTST
104
RCVCLK
103
TRNCLK
102
RES
101
GND
100
VCC
99
/W
98
/R
97
DB7
96
DB6
95
DB5
94
DB4
93
92
91
90
92
91
90
DB1
89
DB0
88
/RES
87
/WR
86
/RD
85
/OPTCS
84
A5
83
A4
82
A3
81
A2
GND
RST
SL32
RCVDT1
/CI1
/CS1
/CD2
DB2
DB3
4 – 13
2) Block diagram
3) Pin description
Pin
NO.
Name
ER-A770
I/O
Description
1
SL00
VCC
ISU
RS-232/UNIT0
channel select
channel select
2
SL01
GND
ISU
3
SL02
GND
ISU
4
SL10
GND
ISU
RS-232/UNIT1
channel select
channel select
5
SL11
GND
ISU
6
SL12
GND
ISU
7
SL20
GND
ISU
RS-232/UNIT2
channel select
channel select
8
SL21
GND
ISU
9
SL22
GND
ISU
10
SL30
GND
ISU
RS-232/UNIT3
channel select
channel select
11
SL31
GND
ISU
12
SL32
GND
ISU
13
/CD0
/DCD1
IS
RS-232 control
signal /CD input
signal /CD input
14
BRK0
BRK1
IS
RS-232 break signal
15
TRNEMP0
TRENMP1
IS
RS-232 transmission
buffer empty signal
buffer empty signal
16
RCVRDY0
RCVRDY1
IS
RS-232 data reception
enable signal
enable signal
17
TRNRDY0
TRNRDY1
IS
RS-232 transmission
enable signal
enable signal
18
/CTS0
/CTS1
IS
RS-232 clear to
send signal
send signal
19
RCVDT0
RCVDT1
IS
RS-232 reception
data signal
data signal
20
VCC
VCC
+5V
21
GND
GND
GND
22
/CI0
/CI1
IS
RS-232 control
signal /CI input
signal /CI input
23
/RTS0
/RTS1
O
RS-232 request to
send signal
send signal
24
/CS0
/CS1
O
RS-232 chip select
signal
signal
25
/CD1
/DCD2
IS
RS-232 control
signal /CD input
signal /CD input
Pin
NO.
Name
ER-A770
I/O
Description
26
BRK1
BRK2
IS
GND
27
TRNEMP1
TRENMP2
IS
GND
28
RCVRDY1
RCVRDY2
IS
GND
29
TRNRDY1
TRNRDY2
IS
GND
30
/CTS1
/CTS2
IS
+5V
31
RCVDT1
RCVDT2
IS
RS-232 reception
data signal
data signal
32
/CI1
/CI2
IS
RS-232 control
signal /CI input
signal /CI input
33
/RTS1
/RTS2
O
RS-232 request to
send signal
send signal
34
/CS1
/CS2
O
RS-232 chip select
signal
signal
35
/CD2
VCC
IS
+5V
36
TRNEMP2
TRENMP3
IS
GND
37
RCVRDY2
RCVRDY3
IS
GND
38
TRNRDY2
TRNRDY3
IS
GND
39
CTS2Z
/CTS3
IS
+5V
40
RCVDT2
RCVDT3
IS
GND
41
/CI2
VCC
IS
+5V
42
/CS2
/CS3
O
NU
43
/CD3
/SINT
IS
RS-232: /CD,
IN-LINE : /P1
IN-LINE : /P1
44
BRK3
GND
IS
GND
45
TRNEMP3
GND
IS
GND
46
RCVRDY3
GND
IS
GND
47
TRNRDY3
GND
IS
GND
48
/CTS3
GND
IS
GND
49
RCVDT3
GND
IS
GND
50
/CI3
GND
IS
GND
51
/CS3
/SRCS
O
RS-232/INLINE chip
select signal
select signal
52
D0
D0
IO
Data bus (CPU)
53
D1
D1
IO
Data bus (CPU)
USART
A
USART
B
USART
C
USART
D
USART
OPC1
DATA BUS
OPC1~USART
OPC2
Common input
BAUD RATE GENERATOR
BAUD RATE GENERATOR
4 – 14
Pin
NO.
Name
ER-A770
I/O
Description
54
D2
D2
IO
Data bus (CPU)
55
D3
D3
IO
Data bus (CPU)
56
GND
GND
GND
57
D4
D4
IO
Data bus (CPU)
58
D5
D5
IO
Data bus (CPU)
59
D6
D6
IO
Data bus (CPU)
60
D7
D7
IO
Data bus (CPU)
61
GND
GND
GND
62
VCC
VCC
+5V
63
X1
NC
O OSI14 NC
64
X2
#
I OSI14 System clock
65
XOUT
CLK_USART
O
Clock (USART)
66
TRCK
NC
O
NC
67
AB0
AH0
O
Address bus for
USART
USART
68
AB1
AH1
O
Address bus for
USART
USART
69
US1CH
GND
IS
GND
70
PX
NC
O
NC
71
/POF
/POFF
IS
POFF signal
72
/RSRQ
/IRQ1
3S
RS232 INTRRUPT
73
/TRV
GND
IS
GND
74
RXDATA0
NC
O
NC
75
TXE
/SRESET
O
INLINE SOFT
RESET
RESET
76
/TRRQ
/TRQ2
3S
INLINE INTRRUPT
77
/TRQ1
/TRQ1
ON6
TIMER INTRRUPT
(RS232)
(RS232)
78
/TRQ2
NC
ON6
TIMER INTRRUPT
(INLINE)
(INLINE)
79
A0
A0
I
Address bus for CPU
80
A1
A1
I
Address bus for CPU
81
A2
A2
I
Address bus for CPU
82
A3
A3
I
Address bus for CPU
83
A4
A4
I
Address bus for CPU
84
A5
A5
I
Address bus for CPU
85
/OPTCS
/OPTCS
I
Option chip select
(from MPCA)
(from MPCA)
86
/RD
/RDO
I
Read signal
(from CPU)
(from CPU)
87
/WR
/WRO
I
Write signal
(from CPU)
(from CPU)
88
/RES
/RES
IS
Reset signal
(from CPU)
(from CPU)
89
DB0
DB0
IO
DATA BUS (USART)
90
DB1
DB1
IO
DATA BUS (USART)
91
DB2
DB2
IO
DATA BUS (USART)
92
DB3
DB3
IO
DATA BUS (USART)
93
GND
GND
GND
94
DB4
DB4
IO
DATA BUS (USART)
95
DB5
DB5
IO
DATA BUS (USART)
96
DB6
DB6
IO
DATA BUS (USART)
97
DB7
DB7
IO
DATA BUS (USART)
98
/R
/RDH
O
Read signal
(to USART)
(to USART)
Pin
NO.
Name
ER-A770
I/O
Description
99
/W
/WRH
O
Write signal
(to USART)
(to USART)
100
VCC
VCC
+5V
101
GND
GND
GND
102
RES
RES USART
O
Reset signal
(to USART)
(to USART)
103
TRNCLK
GND
I
GND
104
RCVCLK
GND
I
GND
105
DBTST
/SRCS
ID
RS-232/INLINE
USART chip select
USART chip select
106
UTST
VCC
ID
+5V
107
/CSA
/CS1
IS
USART_A chip select
108
TRNDTA
TXD1
O
RS-232 transmission
data signal
data signal
109
/DTRA
/DTR1
O
RS-232 data
terminal ready signal
terminal ready signal
110
/RTSA
NC
O
NC
111
RCVDTA
RCVDT1
IS
RS-232 reception
data signal
data signal
112
/CTSA
GND
IS
GND
113
/DSRA
/DSR1
IS
RS-232 data set
ready signal
ready signal
114
TRNRDYA
TRNRDY1
O
RS-232 data
transmission enable
signal
transmission enable
signal
115
RCVRDYA
RCVRDY1
O
RS-232 data reception
enable signal
enable signal
116
TRNEMPA
TRNEMP1
O
RS-232 transmission
buffer empty signal
buffer empty signal
117
SYCBKA
BRK1
IO
Break code
detection signal
detection signal
118
GND
GND GND
119
/CSB
/CS2
IS
USART_B chip select
120
TRNDTB
TXD2
O
NC
121
/DTRB
/DTR2
O
NC
122
/RTSB
NC
O
NC
123
RCVDTB
RCVDT2
IS
GND
124
/CTSB
GND
IS
GND
125
/DSRB
/DSR2
IS
GND
126
TRNRDYB
TRNRDY2
O
NC
127
RCVRDYB
RCVRDY2
O
NC
128
TRNEMPB
TRNEMP2
O
NC
129
SYCBKB
BRK2
IO
NC
130
GND
GND
GND
131
/CSC
/CS3
IS
USART_C chip
select
select
132
TRNDTC
TXD3
O
NC
133
/DTRC
/DTR3
O
NC
134
/RTSC
/RTS3
O
NC
135
RCVDTC
RCVDT3
IS
GND
136
/CTSC
GND
IS
GND
137
/DSRC
/DSR3
IS
GND
138
TRNRDYC
TRNRDY3
O
NC
139
RCVRDYC
RCVRDY3
O
NC
140
TRNEMPC
TRNEMP3
O
NC
141
SYCBKC
NC
IO
NC
4 – 15
Pin
NO.
Name
ER-A770
I/O
Description
142
VCC
VCC
+5V
143
GND
GND
GND
144
/CSD
VCC
IS
+5V
145
TRNDTD
NC
O
NC
146
/DTRD
NC
O
NC
147
/RTSD
NC
O
NC
148
RCVDTD
GND
IS
GND
149
/CTSD
GND
IS
GND
150
/DSRD
GND
IS
GND
151
TRNRDYD
NC
O
NC
152
RCVRDYD
NC
O
NC
153
TRNEMPD
NC
O
NC
154
SYCBKD
NC
IO
NC
155
/WIN
/WRH
I
Write signal
156
/RIN
/RDH
I
Read signal
157
RSLCT0
AH0
I
Address bus
158
RSLCT1
AH1
I
Address bus
159
RST
RES USART
IS
Reset signal
160
MCLK
CLK USART
I
Clock (4.91MHz)
I
TTL input
ID
TTL input with pull down
IS
TTL Schmidt input
ISU
TTL Schmidt input with pull up
IO
TTL I/O
3S
3-state Buffer (6mA)
ON6
Open drain (6mA)
3. Clock generator
1) CPU (HD64151010FX)
Fig. 3-1
Basic clock is supplied from a 19.66 MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) CKDC8 oscillation circuit
Fig. 3-2
Two oscillators are connected to the CKDC8.
The main clock X1 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
The main clock X1 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
This circuit monitors +24V supply voltage.
CPU
(HD64151010FX)
99
98
XTAL
EXTAL
19.66MHz
X4
101
PHAI
37
38
33P
HD404728A91FS
C105
CKDC 8
X2
X1
4.19MHz
4.19MHz
X2
32.768KHz
32.768KHz
2
1
3
41
18P
C106
40
X1
XT2
XT1
R164
330K
330K
+
-
/POFF
3
2
1
4
8
B
IC7A
KIA393F
KIA393F
C37
1000P
1000P
D7
1SS133
C83
1µ 50V
1µ 50V
+
ZD2
MTZ5.1A
MTZ5.1A
R116
9.1KG
9.1KG
R115
15KG
15KG
R118
56K
R117
2.7K
2.7K
R119
2.7K
2.7K
R114
8.2KG
8.2KG
+24V
+5V
POFF
CPU
72
IRQ0
89
RESET (FROM CKDC 8)
STOP (TO CKDC 8)
MPCA7
13
48
1
IR
Q0
54
IN
T0
4 – 16
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